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TP2404NJ PDF预览

TP2404NJ

更新时间: 2024-02-10 00:21:32
品牌 Logo 应用领域
超科 - SUPERTEX /
页数 文件大小 规格书
5页 697K
描述
P-Channel Enhancement-Mode Vertical DMOS FET

TP2404NJ 数据手册

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Supertex inc.  
TP0604  
P-Channel Enhancement-Mode  
Vertical DMOS FET  
Features  
General Description  
Low threshold (-2.4V max.)  
High input impedance  
Low input capacitance (95pF typical)  
Fast switching speeds  
Low on-resistance  
This low threshold, enhancement-mode (normally-off)  
transistor utilizes a vertical DMOS structure and Supertex’s  
well-proven, silicon-gate manufacturing process. This  
combination produces a device with the power handling  
capabilities of bipolar transistors and the high input impedance  
and positive temperature coefficient inherent in MOS devices.  
Characteristic of all MOS structures, this device is free  
from thermal runaway and thermally-induced secondary  
breakdown.  
Free from secondary breakdown  
Low input and output leakage  
Applications  
Logic level interfaces - ideal for TTL and CMOS  
Supertex’s vertical DMOS FETs are ideally suited to a wide  
range of switching and amplifying applications where very  
low threshold voltage, high breakdown voltage, high input  
impedance, low input capacitance, and fast switching speeds  
are desired.  
Solid state relays  
Battery operated systems  
Photo voltaic drives  
Analog switches  
General purpose line drivers  
Telecom switches  
Ordering Information  
Product Summary  
RDS(ON)  
ID(ON)  
Part Number  
Package Option  
Packing  
BVDSS/BVDGS  
VGS(th)  
(V)  
(max) (V)  
(max) (Ω)  
(min) (A)  
TP0604N3-G  
3-Lead TO-92  
1000/Bag  
-40  
2.0  
-2.0  
-2.4  
TP0604N3-G P002  
TP0604N3-G P003  
TP0604N3-G P005 3-Lead TO-92  
TP0604N3-G P013  
2000/Reel Pin Configuration  
TP0604N3-G P014  
DRAIN  
TP2404NW  
TP2404NJ  
TP2404ND  
Die in wafer form  
---  
SOURCE  
Die on adhesive tape ---  
Die in waffle pack ---  
GATE  
TO-92 (N3)  
For packaged products, -G indicates package is RoHS compliant (‘Green’).  
TO-92 taping specifications and winding styles per EIA-468 Standard.  
Devices in Wafer / Die form are RoHS compliant (‘Green’).  
Refer to Die Specification VF57 for layout and dimensions.  
Product Marking  
Absolute Maximum Ratings  
Parameter  
SiTP  
0 6 0 4  
YYWW  
YY = Year Sealed  
WW = Week Sealed  
Value  
BVDSS  
BVDGS  
±20V  
= “Green” Packaging  
Drain-to-source voltage  
Drain-to-gate voltage  
Package may or may not include the following marks: Si or  
TO-92 (N3)  
Gate-to-source voltage  
Operating and storage temperature  
-55OC to +150OC  
Absolute Maximum Ratings are those values beyond which damage to the device  
may occur. Functional operation under these conditions is not implied. Continuous  
operation of the device at the absolute rating level may affect device reliability. All  
voltages are referenced to device ground.  
Doc.# DSFP-TP0604  
C082012  
Supertex inc.  
www.supertex.com  

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