TOP221-227
Oscillator
TOPSwitch-II Family Functional Description (cont.)
The internal oscillator linearly charges and discharges the
internal capacitance between two voltage levels to create a
sawtooth waveform for the pulse width modulator. The oscil-
lator sets the pulse width modulator/current limit latch at the
beginning of each cycle. The nominal frequency of 100 kHz
was chosen to minimize EMI and maximize efficiency in
power supply applications. Trimming of the current reference
improves the frequency accuracy.
Control Voltage Supply
CONTROL pin voltage VC is the supply or bias voltage for the
controller and driver circuitry. An external bypass capacitor
closely connected between the CONTROL and SOURCE
pins is required to supply the gate drive current. The total
amount of capacitance connected to this pin (CT) also sets
the auto-restart timing as well as control loop compensation.
VC is regulated in either of two modes of operation. Hyster-
etic regulation is used for initial start-up and overload opera-
tion. Shunt regulation is used to separate the duty cycle
error signal from the control circuit supply current. During
start-up, CONTROL pin current is supplied from a high-volt-
age switched current source connected internally between
the DRAIN and CONTROL pins. The current source pro-
vides sufficient current to supply the control circuitry as well
as charge the total external capacitance (CT).
Pulse Width Modulator
The pulse width modulator implements a voltage-mode
control loop by driving the output MOSFET with a duty cycle
inversely proportional to the current into the CONTROL pin
which generates a voltage error signal across RE. The error
signal across RE is filtered by an RC network with a typical
corner frequency of 7 kHz to reduce the effect of switching
noise. The filtered error signal is compared with the internal
oscillator sawtooth waveform to generate the duty cycle
waveform. As the control current increases, the duty cycle
decreases. A clock signal from the oscillator sets a latch
which turns on the output MOSFET. The pulse width modu-
lator resets the latch, turning off the output MOSFET. The
maximum duty cycle is set by the symmetry of the internal
oscillator. The modulator has a minimum ON-time to keep
the current consumption of the TOPSwitch independent
of the error signal. Note that a minimum current must be
driven into the CONTROL pin before the duty cycle begins to
change.
The first time VC reaches the upper threshold, the high-
voltage current source is turned off and the PWM modulator
and output transistor are activated, as shown in Figure 5(a).
During normal operation (when the output voltage is regulat-
ed) feedback control current supplies the VC supply current.
The shunt regulator keeps VC at typically 5.7 V by shunting
CONTROL pin feedback current exceeding the required DC
supply current through the PWM error signal sense resistor
RE. The low dynamic impedance of this pin (ZC) sets the
gain of the error amplifier when used in a primary feedback
configuration. The dynamic impedance of the CONTROL
pin together with the external resistance and capacitance
determines the control loop compensation of the power
system.
Gate Driver
The gate driver is designed to turn the output MOSFET on at
a controlled rate to minimize common-mode EMI. The gate
drive current is trimmed for improved accuracy.
If the CONTROL pin total external capacitance (CT) should
discharge to the lower threshold, the output MOSFET is
turned off and the control circuit is placed in a low-current
standby mode. The high-voltage current source turns on
and charges the external capacitance again. Charging
current is shown with a negative polarity and discharging
current is shown with a positive polarity in Figure 6. The
hysteretic auto-restart comparator keeps VC within a window
of typically 4.7 to 5.7 V by turning the high-voltage current
source on and off as shown in Figure 5(b). The auto-restart
circuit has a divide-by-8 counter which prevents the output
MOSFET from turning on again until eight discharge-charge
cycles have elapsed. The counter effectively limits
Error Amplifier
The shunt regulator can also perform the function of an er-
ror amplifier in primary feedback applications. The shunt
regulator voltage is accurately derived from the temperature
compensated bandgap reference. The gain of the error
amplifier is set by the CONTROL pin dynamic impedance.
The CONTROL pin clamps external circuit signals to the VC
voltage level. The CONTROL pin current in excess of the
supply current is separated by the shunt regulator and flows
through RE as a voltage error signal.
Cycle-By-Cycle Current Limit
TOPSwitch power dissipation by reducing the auto-restart
duty cycle to typically 5%. Auto-restart continues to cycle
until output voltage regulation is again achieved.
The cycle by cycle peak drain current limit circuit uses the
output MOSFET ON-resistance as a sense resistor. A current
limit comparator compares the output MOSFET ON-state
drain-source voltage, VDS(ON) with a threshold voltage. High
drain current causes VDS(ON) to exceed the threshold voltage
and turns the output MOSFET off until the start of the next
clock cycle. The current limit comparator threshold voltage
is temperature compensated to minimize variation of the
effective peak current limit due to temperature related
Bandgap Reference
All critical TOPSwitch internal voltages are derived from a
temperature-compensated bandgap reference. This refer-
ence is also used to generate a temperature-compensated
current source which is trimmed to accurately set the oscilla-
tor frequency and MOSFET gate drive current.
changes in output MOSFET RDS(ON)
.
4
Rev. G 08/16
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