TOP200-4/14
TOPSwitch Family Functional Description (cont.)
The first time VC reaches the upper
threshold, the high-voltage current
source is turned off and the PWM
modulator and output transistor are
activated, as shown in Figure 5(a).
During normal operation (when the
output voltage is regulated) feedback
control current supplies the VC supply
current. The shunt regulator keeps VC at
typically 5.7 V by shunting CONTROL
pin feedback current exceeding the
required DC supply current through the
PWMerrorsignalsenseresistorRE. The
low dynamic impedance of this pin (ZC)
sets the gain of the error amplifier when
Bandgap Reference
Gate Driver
All criticalTOPSwitchinternal voltages
are derived from a temperature-
compensated bandgap reference. This
reference is also used to generate a
temperature-compensatedcurrentsource
which is trimmed to accurately set the
oscillator frequency and MOSFET gate
drive current.
The gate driver is designed to turn the
output MOSFET on at a controlled rate
to minimize common-mode EMI. The
gate drive current is trimmed for
improved accuracy.
Error Amplifier
Theshuntregulatorcanalsoperformthe
function of an error amplifier in primary
feedback applications. The shunt
regulator voltage is accurately derived
from the temperature compensated
bandgapreference. Thegainoftheerror
amplifier is set by the CONTROL pin
dynamic impedance. The CONTROL
pin clamps external circuit signals to the
VC voltage level. The CONTROL pin
current in excess of the supply current is
separated by the shunt regulator and
flows through RE as the error signal.
Oscillator
The internal oscillator linearly charges
and discharges the internal capacitance
between two voltage levels to create a
sawtooth waveform for the pulse width
modulator. The oscillator sets the pulse
width modulator/current limit latch at
thebeginningofeachcycle. Thenominal
frequency of 100 kHz was chosen to
minimize EMI and maximize efficiency
inpowersupplyapplications. Trimming
of the current reference improves
oscillator frequency accuracy.
used in
a
primary feedback
configuration. The dynamic impedance
of the CONTROL pin together with the
external resistance and capacitance
determines the control loop
compensation of the power system.
If the CONTROL pin external
capacitance (CT) shoulddischarge tothe
lower threshold, then the output
MOSFET is turned off and the control
circuitisplacedinalow-currentstandby
mode. The high-voltage current source
is turned on and charges the external
capacitance again. Charging current is
shown with a negative polarity and
discharging current is shown with a
positive polarity in Figure 6. The
hystereticauto-restartcomparatorkeeps
VC within a window of typically 4.7 to
5.7Vbyturningthehigh-voltagecurrent
source on and off as shown in Figure
5(b). Theauto-restartcircuithasadivide-
by-8 counter which prevents the output
MOSFET from turning on again until
eight discharge-charge cycles have
elapsed. The counter effectively limits
TOPSwitch power dissipation by
reducing the auto-restart duty cycle to
typically 5%. Auto-restart continues to
cycle until output voltage regulation is
again achieved.
Cycle-By-Cycle Current Limit
The cycle by cycle peak drain current
limit circuit uses the output MOSFET
ON-resistance as a sense resistor. A
current limit comparator compares the
output MOSFET ON-state drain-source
voltage,VDS(ON), withathresholdvoltage.
High drain current causes VDS(ON) to
exceed the threshold voltage and turns
the output MOSFET off until the start of
the next clock cycle. The current limit
comparator threshold voltage is
temperature compensated to minimize
variation of the effective peak current
limit due to temperature related changes
Pulse Width Modulator
The pulse width modulator implements
a voltage-mode control loop by driving
the output MOSFET with a duty cycle
inversely proportional to the current
flowing into the CONTROL pin. The
error signal across RE is filtered by an
RC network with a typical corner
frequency of 7 kHz to reduce the effect
of switching noise. The filtered error
signal is compared with the internal
oscillatorsawtoothwaveformtogenerate
thedutycyclewaveform. Asthecontrol
current increases, the duty cycle
decreases. A clock signal from the
oscillator sets a latch which turns on the
output MOSFET. The pulse width
modulator resets the latch, turning off
the output MOSFET. The maximum
duty cycle is set by the symmetry of the
internal oscillator. The modulator has a
minimum ON-time to keep the current
consumption of the TOPSwitch
independent of the error signal. Note
that a minimum current must be driven
into the CONTROL pin before the duty
cycle begins to change.
in output MOSFET RDS(ON)
.
Theleadingedgeblankingcircuitinhibits
the current limit comparator for a short
time after the output MOSFET is turned
on. The leading edge blanking time has
been set so that current spikes caused by
primary-side capacitances and
secondary-siderectifierreverserecovery
time will not cause premature
termination of the switching pulse.
D
7/96
4
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