TMS320DM6437
Digital Media Processor
www.ti.com
SPRS345D–NOVEMBER 2006–REVISED JUNE 2008
1 TMS320DM6437 Digital Media Processor
1.1 Features
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256K-Bit (32K-Byte) L1P Program
RAM/Cache [Flexible Allocation]
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High-Performance Digital Media Processor
(DM6437)
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2.5-, 2.-, 1.67-, 1.51-, 1.43-ns Instruction
Cycle Time
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640K-Bit (80K-Byte) L1D Data RAM/Cache
[Flexible Allocation]
1M-Bit (128K-Byte) L2 Unified Mapped
RAM/Cache [Flexible Allocation]
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400-, 500-, 600, 660-, 700-MHz C64x+™
Clock Rate
Eight 32-Bit C64x+ Instructions/Cycle
3200, 4000, 4800, 5280, 5600 MIPS
Fully Software-Compatible With C64x
Commercial and Automotive (Q or S suffix)
Grades
Low-Power Device (L suffix)
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Supports Little Endian Mode Only
Video Processing Subsystem (VPSS)
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Front End Provides:
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CCD and CMOS Imager Interface
BT.601/BT.656 Digital YCbCr 4:2:2
(8-/16-Bit) Interface
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VelociTI.2™ Extensions to VelociTI™
Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+™ DSP Core
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Preview Engine for Real-Time Image
Processing
Glueless Interface to Common Video
Decoders
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Eight Highly Independent Functional Units
With VelociTI.2 Extensions:
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Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
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Histogram Module
Auto-Exposure, Auto-White Balance and
Auto-Focus Module
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Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
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Resize Engine
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Resize Images From 1/4x to 4x
Separate Horizontal/Vertical Control
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Back End Provides:
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Load-Store Architecture With Non-Aligned
Support
64 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
Additional C64x+™ Enhancements
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Hardware On-Screen Display (OSD)
Four 54-MHz DACs for a Combination of
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Composite NTSC/PAL Video
Luma/Chroma Separate Video
(S-video)
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Component (YPbPr or RGB) Video
(Progressive)
Protected Mode Operation
Exceptions Support for Error Detection
and Program Redirection
Hardware Support for Modulo Loop
Auto-Focus Module Operation
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Digital Output
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8-/16-bit YUV or up to 24-Bit RGB
HD Resolution
Up to 2 Video Windows
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C64x+ Instruction Set Features
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External Memory Interfaces (EMIFs)
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Byte-Addressable (8-/16-/32-/64-Bit Data)
8-Bit Overflow Protection
Bit-Field Extract, Set, Clear
Normalization, Saturation, Bit-Counting
VelociTI.2 Increased Orthogonality
C64x+ Extensions
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32-Bit DDR2 SDRAM Memory Controller
With 256M-Byte Address Space (1.8-V I/O)
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Supports up to 333-MHz (data rate) Bus
and Interfaces With DDR2-400 SDRAM
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Asynchronous 8-Bit Wide EMIF (EMIFA)
With up to 64M-Byte Address Reach
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Compact 16-bit Instructions
Additional Instructions to Support
Complex Multiplies
Flash Memory Interfaces
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NOR (8-Bit-Wide Data)
NAND (8-Bit-Wide Data)
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C64x+ L1/L2 Memory Architecture
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2008, Texas Instruments Incorporated
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