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TM497MBK36Q-60

更新时间： 2024-01-05 11:05:35
品牌 Logo 应用领域
德州仪器 - TI 动态存储器内存集成电路
页数 文件大小 规格书
9页 118K
描述
4MX36 FAST PAGE DRAM MODULE, 60ns, SMA72, SIMM-72

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TM497MBK36Q-60 技术参数

生命周期：Obsolete零件包装代码：SIMM
包装说明：SIMM-72针数：72
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.24风险等级：5.84
Is Samacsys：N访问模式：FAST PAGE
最长访问时间：60 ns其他特性：RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
I/O 类型：COMMONJESD-30 代码：R-XSMA-N72
内存密度：150994944 bit内存集成电路类型：FAST PAGE DRAM MODULE
内存宽度：36功能数量：1
端口数量：1端子数量：72
字数：4194304 words字数代码：4000000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：4MX36
输出特性：3-STATE封装主体材料：UNSPECIFIED
封装代码：SIMM封装等效代码：SSIM72
封装形状：RECTANGULAR封装形式：MICROELECTRONIC ASSEMBLY
电源：5 V认证状态：Not Qualified
刷新周期：2048座面最大高度：25.527 mm
自我刷新：NO最大待机电流：0.012 A
子类别：DRAMs最大压摆率：1.3 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：COMMERCIAL
端子形式：NO LEAD端子节距：1.27 mm
端子位置：SINGLEBase Number Matches：1

TM497MBK36Q-60 数据手册

 浏览型号TM497MBK36Q-60的Datasheet PDF文件第2页浏览型号TM497MBK36Q-60的Datasheet PDF文件第3页浏览型号TM497MBK36Q-60的Datasheet PDF文件第4页浏览型号TM497MBK36Q-60的Datasheet PDF文件第5页浏览型号TM497MBK36Q-60的Datasheet PDF文件第6页浏览型号TM497MBK36Q-60的Datasheet PDF文件第7页 
TM497MBK36A, TM497MBK36Q  
4194304 BY 36-BIT  
DYNAMIC RAM MODULE  
SMMS446C – DECEMBER 1992 – REVISED JUNE 1995  
Organization . . . 4 194 304 × 36  
Performance Ranges:  
ACCESS ACCESS ACCESS READ  
Single 5-V Power Supply (±10% Tolerance)  
TIME  
TIME  
TIME  
OR  
72-Pin Single-In-Line Memory Module  
(SIMM) for Use With Sockets  
t
t
t
WRITE  
CYCLE  
(MIN)  
RAC  
CAC  
AA  
(MAX)  
(MAX)  
(MAX)  
Utilizes Eight 16-Megabit DRAMs in Plastic  
Small-Outline J-Lead (SOJ) Packages and  
Four 4-Megabit DRAMs in Plastic  
’497MBK36A-60 60 ns  
’497MBK36A-70 70 ns  
’497MBK36A-80 80 ns  
15 ns  
18 ns  
20 ns  
30 ns  
35 ns  
40 ns  
110 ns  
130 ns  
150 ns  
Small-Outline J-Lead (SOJ) Packages  
Low Power Dissipation  
Long Refresh Period  
Operating Free-Air Temperature Range  
†
32 ms (2048 Cycles)  
0°C to 70°C  
All Inputs, Outputs, Clocks Fully TTL  
Compatible  
Presence Detect  
‡
Gold-Tabbed Version Available:  
TM497MBK36A  
Common CAS Control for Nine Common  
Data-In and Data-Out Lines in Four Blocks  
Tin-Lead (Solder) Tabbed Version  
Available: TM497MBK36Q  
Separate RAS Control for Eighteen Data-In  
and Data-Out Lines in Two Blocks  
3-State Output  
description  
The TM497MBK36A is a 16M-byte dynamic random-access memory (DRAM) organized as four times  
4194304 × 9 (bit 9 is generally used for parity) in a 72-pin leadless single-in-line memory module (SIMM). The  
SIMM is composed of eight TMS417400DJ, 4194304× 4-bit DRAMs, each in 24/26-lead plastic SOJ packages,  
and four TMS44100DJ, 4194304 × 1-bit DRAMs, each in 20/26-lead plastic SOJ packages mounted on a  
substrate with decoupling capacitors. Each TMS417400DJ and TMS44100DJ is described in the TMS417400  
and TMS44100 data sheets (respectively).  
The TM497MBK36A is available in a double-sided BK leadless module for use with sockets. The  
TM497MBK36AfeaturesRASaccesstimesof60ns, 70ns, and80ns. Thisdeviceischaracterizedforoperation  
from 0°C to 70°C.  
operation  
The TM497MBK36A operates as eight TMS417400DJs and four TMS44100DJs connected as shown in the  
functional block diagram and Table 1. Refer to the TMS417400 and TMS44100 data sheets for details of  
operation. The common I/O feature dictates the use of early write cycles to prevent contention on D and Q.  
refresh  
The refresh period is extended to 32 ms and, during this period, each of the 2048 rows must be strobed with  
RAS in order to retain data. Address line A10 must be used as most significant refresh address line (lowest  
frequency) to assure correct refresh for both TMS417400 and TMS44100. A0–A9 address lines must be  
refreshed every 16 ms as required by the TMS44100 DRAM. CAS can remain high during the refresh sequence  
to conserve power.  
power up  
To achieve proper operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is  
required after full V level is achieved. These eight initialization cycles need to include at least one refresh  
CC  
[RAS-only or CAS-before-RAS (CBR)] cycle.  
†
‡
A0–A9 address lines must be refreshed every 16 ms.  
Part numbers in this data sheet refer only to the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...9

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与TM497MBK36Q-60相关器件

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TM497MBM36A-60 TI 4MX36 FAST PAGE DRAM MODULE, 60ns, SMA72, SIMM-72

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TM497MBM36A-80 TI 4MX36 FAST PAGE DRAM MODULE, 80ns, SMA72, SIMM-72

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TM497MBM36Q-60 TI 4MX36 FAST PAGE DRAM MODULE, 60ns, SMA72, SIMM-72

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TM497MBM36Q-70 TI 4MX36 FAST PAGE DRAM MODULE, 70ns, SMA72, SIMM-72

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TM497MBM36Q-80 TI 4MX36 FAST PAGE DRAM MODULE, 80ns, SMA72, SIMM-72

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