Datasheet > TM497EU9

TM497EU9

更新时间： 2022-11-26 04:34:05

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
7页	90K
描述
4194304-WORD BY 9-BIT DYNAMIC RAM MODULE

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TM497EU9 数据手册

TM497EU9

4194304-WORD BY 9-BIT

DYNAMIC RAM MODULE

SMMS499A – FEBRUARY 1994 – REVISED JUNE 1995

operation

The TM497EU9 operates as two TMS417400DJs and one TMS44100DJ connected as shown in the functional

block diagram (refer to the TMS417400 and TMS44100 data sheets for details of their operation). The common

I/O feature of the TM497EU9 dictates the use of early write cycles to prevent contention on D and Q.

refresh

The refresh period is extended to 32 ms and, during this period, each of the 2048 rows must be strobed with

RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power. In addition,

the ten least significant row addresses (A0–A9) must be refreshed every 16 ms as required by the TMS44100.

power up

To achieve proper operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is

required after full V

(RAS-only or CBR) cycle.

level is achieved. These eight initialization cycles need to include at least one refresh

single-in-line memory module and components

PC substrate: 1,27 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage

Bypass capacitors: Multilayer ceramic

Contact area for socketable devices: Nickel plate and solder plate over copper

functional block diagram

4M × 4

A0–A10 DQ1

A0–A10

RAS

CAS

DQ1

DQ2

DQ3

DQ4

RAS

CAS

DQ2

DQ3

DQ4

4M × 4

A0–A10 DQ1

DQ5

DQ6

DQ7

DQ8

RAS

CAS

DQ2

DQ3

DQ4

4M × 1

A0–A10

RAS

CAS

CAS9

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

123 4 5 6 7

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