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TLV5619-EP PDF预览

TLV5619-EP

更新时间： 2024-11-19 12:47:11
品牌 Logo 应用领域
德州仪器 - TI 转换器
页数 文件大小 规格书
25页 923K
描述
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

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中文翻译

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TLV5619-EP 数据手册

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SGLS124A − JULY 2002 − REVISED DECEMBER 2003  
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
applications  
D
D
D
Battery Powered Test Instruments  
Digital Offset and Gain Adjustment  
D
D
D
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Extended Temperature Performance of  
−40°C to 125°C  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
Battery Operated/Remote Industrial  
Controls  
D
D
D
D
D
Machine and Motion Control Devices  
Cordless and Wireless Telephones  
Speech Synthesis  
Enhanced Product Change Notification  
†
Qualification Pedigree  
Communication Modulators  
Arbitrary Waveform Generation  
Single Supply 2.7-V to 5.5-V Operation  
0.4 LSB Differential Nonlinearity (DNL),  
1.5 LSB Integral Nonlinearity (INL)  
D
D
D
D
D
12-Bit Parallel Interface  
Compatible With TMS320 DSP  
Internal Power On Reset  
Settling Time 1 µs Typ  
Low Power Consumption:  
− 8 mW for 5-V Supply  
− 4.3 mW for 3-V Supply  
DW PACKAGE  
(TOP VIEW)  
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D11  
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D0  
CS  
WE  
LDAC  
PD  
GND  
OUT  
REFIN  
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Reference Input Buffers  
Voltage Output  
Monotonic Over Temperature  
Asynchronous Update  
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DD  
†
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
description  
The TLV5619 is a 12-bit voltage output DAC with a microprocessor and TMS320 compatible parallel interface.  
The 12 data bits are double buffered so that the output can be updated asynchronously using the LDAC pin.  
During normal operation, the device dissipates 8 mW at a 5-V supply and 4.3 mW at a 3-V supply. The power  
consumption can be lowered to 50 nW by setting the DAC to power-down mode.  
The output voltage is buffered by a ×2 gain rail-to-rail amplifier, which features a Class A output stage to improve  
stability and reduce settling time.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
T
A
PACKAGE  
−40°C to 125°C  
SOP − DW Tape and reel  
TLV5619QDWREP  
TLV5619QEP  
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2002 − 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...25

中文翻译

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与TLV5619-EP相关器件

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 		2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
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 		12-Bit, Single Channel DAC, Parallel, Voltage Out, Low Power, Asynchronous Update 20-SOIC
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 		12-Bit, Single Channel DAC, Parallel, Voltage Out, Low Power, Asynchronous Update 20-SOIC
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TLV5619IPWR TI

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 		12-Bit, Single Channel DAC, Parallel, Voltage Out, Low Power, Asynchronous Update 20-TSSOP
TLV5619IPWRG4 TI

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 		12-Bit, Single Channel DAC, Parallel, Voltage Out, Low Power, Asynchronous Update 20-TSSOP
TLV5619PW TI

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 		2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
TLV5619QDW TI

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 		2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
TLV5619QDWG4 TI

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 		12 位单通道并行 DAC，具有电压输出、低功耗和异步更新 | DW | 20
TLV5619QDWREP TI

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 		2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

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