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TLV5606IDGK PDF预览

TLV5606IDGK

更新时间: 2024-01-16 19:28:06
品牌 Logo 应用领域
德州仪器 - TI 转换器
页数 文件大小 规格书
23页 443K
描述
2.7 V TO 5.5 V LOW POWER 10-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

TLV5606IDGK 数据手册

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ꢀꢁꢂ ꢃꢄ ꢅꢄ  
ꢆ ꢇꢈ ꢉꢂ ꢀ ꢊ ꢃ ꢇꢃ ꢉꢂ ꢁ ꢊ ꢋ ꢌꢊ ꢋ ꢍꢎ ꢏ ꢅ ꢉꢐꢑ ꢀ ꢒꢑ ꢓꢑ ꢀꢔꢁ ꢉꢀꢊ ꢉꢔ ꢕ ꢔꢁ ꢊꢓ  
ꢖꢊ ꢕꢂꢍ ꢎꢀ ꢍꢎꢗ ꢋ ꢑꢀ ꢘ ꢌꢊ ꢋ ꢍ ꢎ ꢒ ꢊꢋ ꢕ  
SLAS259B − DECEMBER 1999 − REVISED APRIL 2004  
D
Buffered High-Impedance Reference Input  
features  
D
Voltage Output Range . . . 2 Times the  
Reference Input Voltage  
D
D
10-Bit Voltage Output DAC  
Programmable Settling Time vs Power  
Consumption  
D
Monotonic Over Temperature  
Available in MSOP Package  
3 µs in Fast Mode  
D
9 µs in Slow Mode  
applications  
D
Ultra Low Power Consumption:  
900 µW Typ in Slow Mode at 3 V  
2.1 mW Typ in Fast Mode at 3 V  
D
D
D
D
D
Digital Servo Control Loops  
Digital Offset and Gain Adjustment  
Industrial Process Control  
D
D
D
Differential Nonlinearity . . . <0.2 LSB Typ  
Compatible With TMS320 and SPI Serial  
Ports  
Machine and Motion Control Devices  
Mass Storage Devices  
Power-Down Mode (10 nA)  
D OR DGK PACKAGE  
(TOP VIEW)  
description  
The TLV5606 is a 10-bit voltage output digital-to-  
analog converter (DAC) with a flexible 4-wire  
serial interface. The 4-wire serial interface allows  
glueless interface to TMS320, SPI, QSPI, and  
Microwire serial ports. The TLV5606 is pro-  
grammed with a 16-bit serial string containing 4  
control and 10 data bits. Developed for a wide  
range of supply voltages, the TLV5606 can  
operate from 2.7 V to 5.5 V.  
DIN  
SCLK  
CS  
V
DD  
OUT  
1
2
3
4
8
7
6
5
REFIN  
AGND  
FS  
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB  
output stage to improve stability and reduce settling time. The settling time of the DAC is programmable to allow  
the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within  
the 16-bit serial input string. A high-impedance buffer is integrated on the REFIN terminal to reduce the need  
for a low source impedance drive to the terminal.  
Implemented with a CMOS process, the TLV5606 is designed for single supply operation from 2.7 V to 5.5 V.  
The device is available in an 8-terminal SOIC package. The TLV5606C is characterized for operation from 0°C  
to 70°C. The TLV5606I is characterized for operation from 40°C to 85°C.  
AVAILABLE OPTIONS  
PACKAGE  
MSOP  
(DGK)  
T
A
SMALL OUTLINE  
(D)  
0°C to 70°C  
TLV5606CD  
TLV5606ID  
TLV5606CDGK  
TLV5606IDGK  
40°C to 85°C  
Available in tape and reel as the TLV5606CDR, TLV5606IDR,  
TLV5606CDGKR, and the TLV5606IDGKR  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002−2004, Texas Instruments Incorporated  
ꢌꢞ ꢝ ꢩꢤꢣ ꢡ ꢢ ꢣ ꢝꢛ ꢜꢝ ꢞ ꢟ ꢡ ꢝ ꢢ ꢦꢥ ꢣ ꢚꢜ ꢚꢣꢠ ꢡꢚ ꢝꢛꢢ ꢦꢥ ꢞ ꢡꢪ ꢥ ꢡꢥ ꢞ ꢟꢢ ꢝꢜ ꢀꢥꢫ ꢠꢢ ꢑꢛꢢ ꢡꢞ ꢤꢟ ꢥꢛꢡ ꢢ  
ꢢ ꢡ ꢠ ꢛꢩ ꢠ ꢞꢩ ꢬ ꢠ ꢞꢞ ꢠ ꢛ ꢡꢭꢇ ꢌꢞ ꢝ ꢩꢤꢣ ꢡꢚꢝꢛ ꢦꢞ ꢝꢣ ꢥꢢ ꢢꢚ ꢛꢮ ꢩꢝꢥ ꢢ ꢛꢝꢡ ꢛꢥ ꢣꢥ ꢢꢢ ꢠꢞ ꢚꢨ ꢭ ꢚꢛꢣ ꢨꢤꢩ ꢥ  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢮ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢇ  
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