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TLV5591DWR PDF预览

TLV5591DWR

更新时间： 2024-02-06 04:33:49
品牌 Logo 应用领域
德州仪器 - TI 电信光电二极管电信集成电路
页数 文件大小 规格书
4页 54K
描述
SPECIALTY TELECOM CIRCUIT, PDSO28, SOIC-28

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TLV5591DWR 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：28
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84JESD-30 代码：R-PDSO-G28
长度：17.91 mm功能数量：1
端子数量：28封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE认证状态：Not Qualified
座面最大高度：2.65 mm表面贴装：YES
电信集成电路类型：TELECOM CIRCUIT端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：7.52 mmBase Number Matches：1

TLV5591DWR 数据手册

 浏览型号TLV5591DWR的Datasheet PDF文件第2页浏览型号TLV5591DWR的Datasheet PDF文件第3页浏览型号TLV5591DWR的Datasheet PDF文件第4页 
TLV5591  
SEMICONDUCTOR SIGNAL PROCESSOR  
SLWS024– AUGUST 1995  
DW PACKAGE  
(TOP VIEW)  
FLEX Paging Protocol Signal Processor  
FLEX Roaming, Fragmentation, and Group  
Messaging Support  
NC  
NC  
V
1
28  
27  
FLEX Time-of-Day Stamping Support  
V
2
DD  
SS  
16 Address Words support any  
Combination of Long (2 Word) and Short  
(1 Word) Addresses  
RST  
3
26 XTAL  
LO BAT  
EXTS0  
EXTS1  
S0  
4
25 EXTAL  
5
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
CLKOUT  
SS  
16 Temporary Address Words Support  
Group Messaging  
6
7
SCK  
S1  
8
SDI  
1600, 3200, and 6400 Bits per Second  
Decoding  
S2  
9
SDO  
I/O RDY  
ATTN  
NC  
10  
11  
12  
13  
14  
S3  
Any Phase (1, 2, and 4) Decoding  
S4  
Serial Peripheral Interface Security Circuit  
Deters Unauthorized Reconfigurations  
S5  
V
V
SS  
DD  
2.0 Volt to 3.3 Volt Operation  
NC  
NC  
Allows Low Current STOP Mode Operation  
of Host Processor  
Uses standard Serial Peripheral Interface  
(SPI) in Slave Mode  
32-bit Packets for Bidirectional  
Communications over the Serial Peripheral  
Interface  
Universal Receiver Control Supports many  
RF Integrated Circuits  
Programmable Low Battery Monitoring  
description  
The TLV5591 signal processor is a FLEX signal processor that takes full advantage of the Motorola FLEX  
paging protocol. This low-current device operates at synchronous data rates of 1600, 3200, and 6400 bits per  
second (bps) using a 76.8 kHz oscillator. This device is readily integrated with standard off-the-shelf electronic  
pager components thereby reducing start-up costs associated with pager manufacturing. An industry standard  
serial peripheral interface (SPI) transports simultaneous bidirectional 32-bit data packets between the TLV5591  
and the host processor.  
As a FLEX protocol decoder, the internal TLV5591 receiver control component makes use of 6-stage warm-up,  
2-stage locking, and 3-stage warm-down sequences. This control information is passed to the receiver using  
sixprogrammabledataoutputlines. Warm-upcontrolallowstestingofbatterycondition, settingoutputlinestate,  
RF receiver power-on time, and other elements of a pager. The 2-stage locking sequence handles requirements  
associated with received FLEX signal baud rate changes. The warm-down control sets the program selectable  
time period when signal processing is complete, and the receiver can power-off. Battery condition can be  
checked, and the output line state can be changed under warm down control.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
FLEX and Motorola are trademarks of Motorola, Inc.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234

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