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TLV5580CPWR PDF预览

TLV5580CPWR

更新时间： 2024-02-26 05:31:03
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管转换器
页数 文件大小 规格书
38页 1181K
描述
1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28, GREEN, PLASTIC, TSSOP-28

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TLV5580CPWR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：TSSOP, TSSOP28,.25针数：28
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.72
最大模拟输入电压：3.5 V最小模拟输入电压：0.8 V
最长转换时间：0.0125 µs转换器类型：ADC, PROPRIETARY METHOD
JESD-30 代码：R-PDSO-G28长度：9.7 mm
最大线性误差 (EL)：0.9375%模拟输入通道数量：1
位数：8功能数量：1
端子数量：28最高工作温度：70 °C
最低工作温度：输出位码：BINARY
输出格式：PARALLEL, 8 BITS封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP28,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
认证状态：Not Qualified采样速率：80 MHz
采样并保持/跟踪并保持：SAMPLE座面最大高度：1.2 mm
子类别：Analog to Digital Converters标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm

TLV5580CPWR 数据手册

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ꢀꢁꢂ ꢃꢃ ꢄꢅ  
ꢄ ꢆꢇꢈ ꢀꢉ ꢄ ꢅ ꢊ ꢋꢌꢋ ꢁ ꢍ ꢎꢆꢌꢍ ꢎ ꢏꢐ ꢑꢒ ꢓ ꢔꢍꢕ ꢂ ꢏꢐ ꢀꢏ ꢐ  
www.ti.com  
SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003  
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS WITH F  
MSPS AND USE OF EXTERNAL VOLTAGE REFERENCES (unless otherwise noted)  
= 80  
CLK  
DC ACCURACY  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Integral nonlinearity (INL), best-fit  
Differential nonlinearity (DNL)  
Zero error  
Internal references (see Note 1)  
Internal references (see Note 2)  
T
= −40°C to 85°C  
= −40°C to 85°C  
−2.4  
−1  
1
2.4  
1.3  
5
LSB  
LSB  
%FS  
%FS  
A
T
A
0.6  
AV  
DD  
= DV  
DD  
= 3.3 V, DRV = 3 V See Note 3  
DD  
Full scale error  
5
1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero  
occurs 1/2 LSB before the first code transition. The full−scale point is defined as a level 1/2 LSB beyond the last code transition. The deviation  
is measured from the center of each particular code to the true straight line between these two endpoints.  
2. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure indicates  
how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under test (i.e., (last transition  
n
level − first transition level) ÷ (2 − 2)). Using this definition for DNL separates the effects of gain and offset error. A minimum DNL better than −1  
LSB ensures no missing codes.  
3. Zero error is defined as the difference in analog input voltage − between the ideal voltage and the actual voltage − that will switch the ADC output  
from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the bottom reference level. The  
voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels (256).  
Full-scale error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch the ADC  
output from code 254 to code 255. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5 LSB from the top reference  
level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels  
(256).  
ANALOG INPUT  
PARAMETER  
Input capacitance  
TEST CONDITIONS  
TEST CONDITIONS  
MIN  
MIN  
TYP  
MAX  
MAX  
UNIT  
C
4
pF  
I
REFERENCE INPUT (AV  
= DV  
= DRV  
= 3.6 V)  
DD  
DD  
DD  
PARAMETER  
Reference input resistance  
Reference input current  
TYP  
200  
5
UNIT  
Ω
R
ref  
I
mA  
ref  
REFERENCE OUTPUTS  
PARAMETER  
Reference top offset voltage  
Reference bottom offset voltage  
TEST CONDITIONS  
Absolute min/max values valid  
MIN  
2.07  
1.09  
TYP  
MAX  
2.21  
1.21  
UNIT  
V
V
V
2 + [(AV  
− 3) ÷ 2]  
− 3) ÷ 2]  
(REFTO)  
DD  
and tested for AV = 3.3 V  
1 + [(AV  
V
DD  
(REFBO)  
DD  
7
1...567891011...38

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