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TLV5580CDW PDF预览

TLV5580CDW

更新时间： 2024-02-14 20:36:38
品牌 Logo 应用领域
德州仪器 - TI 光电二极管转换器
页数 文件大小 规格书
34页 531K
描述
8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

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TLV5580CDW 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：GREEN, PLASTIC, SOIC-28针数：28
Reach Compliance Code：unknown风险等级：5.65
最大模拟输入电压：3.5 V最小模拟输入电压：0.8 V
最长转换时间：0.0125 µs转换器类型：ADC, PROPRIETARY METHOD
JESD-30 代码：R-PDSO-G28JESD-609代码：e4
长度：17.9 mm最大线性误差 (EL)：0.9375%
湿度敏感等级：1模拟输入通道数量：1
位数：8功能数量：1
端子数量：28最高工作温度：70 °C
最低工作温度：输出位码：BINARY
输出格式：PARALLEL, 8 BITS封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
采样速率：80 MHz采样并保持/跟踪并保持：SAMPLE
座面最大高度：2.65 mm标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：NICKEL PALLADIUM GOLD
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.5 mmBase Number Matches：1

TLV5580CDW 数据手册

 浏览型号TLV5580CDW的Datasheet PDF文件第4页浏览型号TLV5580CDW的Datasheet PDF文件第5页浏览型号TLV5580CDW的Datasheet PDF文件第6页浏览型号TLV5580CDW的Datasheet PDF文件第8页浏览型号TLV5580CDW的Datasheet PDF文件第9页浏览型号TLV5580CDW的Datasheet PDF文件第10页 
TLV5580  
8-BIT, 80 MSPS LOW-POWER A/D CONVERTER  
SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999  
electrical characteristics over recommended operating conditions with f  
of external voltage references (unless otherwise noted)  
= 80 MSPS and use  
CLK  
dc accuracy  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
±1  
MAX  
2
UNIT  
LSB  
LSB  
LSB  
%FS  
%FS  
T
= 25°C  
–2  
–2.4  
–1  
A
Integral nonlinearity (INL), best-fit  
Internal references (see Note 1)  
Internal references (see Note 2),  
T
A
= –40°C to 85°C  
= –40°C to 85°C  
±1  
2.4  
1.3  
5
Differential nonlinearity (DNL)  
Zero error  
T
A
±0.6  
AV  
DD  
= DV  
= 3.3 V, DRV = 3 V See Note 3  
DD  
DD  
Full scale error  
5
NOTES: 1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero  
occurs 1/2 LSB before the first code transition. The full–scale point is defined as a level 1/2 LSB beyond the last code transition.  
The deviation is measured from the center of each particular code to the true straight line between these two endpoints.  
2. AnidealADCexhibitscodetransitionsthatareexactly1LSBapart. DNListhedeviationfromthisidealvalue.Thereforethismeasure  
indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under  
n
test (i.e., (last transition level – first transition level) ÷ (2 – 2)). Using this definition for DNL separates the effects of gain and offset  
error. A minimum DNL better than –1 LSB ensures no missing codes.  
3. Zero error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch  
the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the  
bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by  
the number of ADC output levels (256).  
Full-scaleerrorisdefinedasthedifferenceinanaloginputvoltage–betweentheidealvoltageandtheactualvoltage–thatwillswitch  
the ADC output from code 254 to code 255. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5  
LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references  
divided by the number of ADC output levels (256).  
analog input  
PARAMETER  
Input capacitance  
TEST CONDITIONS  
TEST CONDITIONS  
MIN  
MIN  
TYP  
MAX  
MAX  
UNIT  
C
4
pF  
I
reference input (AV  
= DV  
= DRV  
= 3.6 V)  
DD  
DD  
DD  
PARAMETER  
Reference input resistance  
Reference input current  
TYP  
200  
5
UNIT  
Ω
R
ref  
I
mA  
ref  
reference outputs  
PARAMETER  
TEST CONDITIONS  
Absolute min/max values valid  
and tested for AV = 3.3 V  
MIN  
2.07  
1.09  
TYP  
MAX  
2.21  
1.21  
UNIT  
V
V
V
Reference top offset voltage  
2 + [(AV  
– 3) ÷ 2]  
– 3) ÷ 2]  
(REFTO)  
DD  
DD  
Reference bottom offset voltage  
1 + [(AV  
V
(REFBO)  
DD  
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1...45678910...34

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