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TLV5580CDW PDF预览

TLV5580CDW

更新时间: 2024-02-12 06:45:47
品牌 Logo 应用领域
德州仪器 - TI 光电二极管转换器
页数 文件大小 规格书
34页 531K
描述
8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

TLV5580CDW 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:GREEN, PLASTIC, SOIC-28针数:28
Reach Compliance Code:unknown风险等级:5.65
最大模拟输入电压:3.5 V最小模拟输入电压:0.8 V
最长转换时间:0.0125 µs转换器类型:ADC, PROPRIETARY METHOD
JESD-30 代码:R-PDSO-G28JESD-609代码:e4
长度:17.9 mm最大线性误差 (EL):0.9375%
湿度敏感等级:1模拟输入通道数量:1
位数:8功能数量:1
端子数量:28最高工作温度:70 °C
最低工作温度:输出位码:BINARY
输出格式:PARALLEL, 8 BITS封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
采样速率:80 MHz采样并保持/跟踪并保持:SAMPLE
座面最大高度:2.65 mm标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

TLV5580CDW 数据手册

 浏览型号TLV5580CDW的Datasheet PDF文件第1页浏览型号TLV5580CDW的Datasheet PDF文件第2页浏览型号TLV5580CDW的Datasheet PDF文件第3页浏览型号TLV5580CDW的Datasheet PDF文件第5页浏览型号TLV5580CDW的Datasheet PDF文件第6页浏览型号TLV5580CDW的Datasheet PDF文件第7页 
TLV5580  
8-BIT, 80 MSPS LOW-POWER A/D CONVERTER  
SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999  
Terminal Functions  
TERMINAL  
NAME  
AIN  
I/O  
DESCRIPTION  
NO.  
26  
I
I
Analog input  
AV  
16, 27  
18, 23, 28  
17  
Analog supply voltage  
Analog ground  
DD  
SS  
AV  
I
BG  
O
Band gap reference voltage. A 1 µF capacitor (with an optional 0.1 µF capacitor in parallel) should be  
connected between this terminal and AV for external filtering.  
SS  
Clock input. The input is sampled on each rising edge of CLK.  
Common mode level. This voltage is equal to (AV – AV ) ÷ 2. An external 0.1 µF capacitor should be  
CLK  
CML  
12  
25  
I
O
DD SS  
connected between this terminal and AV  
.
SS  
D0 – D7  
2 – 9  
1
O
I
Data outputs. D7 is the MSB  
DRV  
DRV  
Supply voltage for digital output drivers  
Ground for digital output drivers  
Digital supply voltage  
DD  
SS  
10  
14  
13  
11  
I
DV  
OE  
DV  
I
DD  
I
Output enable. When high the D0 – D7 outputs go in high-impedance mode.  
Digital ground  
I
SS  
PWDN_REF  
24  
I
Power down for internal reference voltages. A high on this terminal will disable the internal reference  
circuit.  
REFBI  
21  
I
Reference voltage bottom input. The voltage at this terminal defines the bottom reference voltage for the  
ADC. It can be connected to REFBO or to an externally generated reference level. Sufficient filtering  
should be applied to this input. The use a 0.1 µF capacitor connected between REFBI and AV  
recommended. Additionaly, a 0.1 µF capacitor can be connected between REFTI and REFBI.  
is  
SS  
REFBO  
REFTI  
22  
20  
O
I
Reference voltage bottom output. An internally generated reference is available at this terminal. It can be  
connected to REFBI or left unconnected. A 1 µF capacitor between REFBO and AV  
sufficient decoupling required for this output.  
will provide  
SS  
Reference voltage top input. The voltage at this terminal defines the top reference voltage for the ADC.  
It can be connected to REFTO or to an externally generated reference level. Sufficient filtering should be  
appliedtothisinput.Theuseofa0.1µFcapacitorbetweenREFTIandAV isrecommended. Additionaly,  
SS  
a 0.1 µF capacitor can be connected between REFTI and REFBI.  
REFTO  
STBY  
19  
15  
O
I
Reference voltage top output. An internally generated reference is available at this terminal. It can be  
connectedtoREFTIorleftunconnected.A1µFcapacitorbetweenREFTOandAV willprovidesufficient  
SS  
decoupling required for this output.  
Standby input. A high level on this input enables a powerdown mode.  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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