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TLE9350BSJ

更新时间: 2024-03-03 10:10:30
品牌 Logo 应用领域
英飞凌 - INFINEON /
页数 文件大小 规格书
30页 812K
描述
The TLE9350BSJ is a high speed CAN transceiver, used in HS CAN systems for automotive applications

TLE9350BSJ 数据手册

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TLE9350BSJ  
High speed CAN FD transceiver  
The TLE9350BSJ operates as an interface between the CAN controller and the physical bus medium. A HS CAN  
is a two wire differential network which allows data transmission rates up to 5 Mbit/s. The characteristics for  
a HS CAN are the two signal states on the CAN bus: dominant and recessive (see Figure 3).  
The CANH and CANL pins are the interface to the CAN bus and both pins operate as an input and output  
simultaneously. The RxD and TxD pins are the interface to the microcontroller. The pin TxD is the serial data  
input from the CAN controller, the RxD pin is the serial data output to the CAN controller. As shown in Figure 1,  
the TLE9350BSJ includes a receiver and a transmitter unit, allowing the transceiver to send data to the bus  
medium and monitor the data from the bus medium at the same time. The TLE9350BSJ converts the serial  
data stream which is available on the transmit data input TxD, into a differential output signal on the CAN bus,  
provided by the CANH and CANL pins. The receiver stage of the TLE9350BSJ monitors the data on the CAN bus  
and converts them to a serial, single-ended signal on the RxD output pin. A "low" signal on the TxD pin creates  
a dominant signal on the CAN bus, followed by a logical "low" signal on the RxD pin (see Figure 3). The feature  
of broadcasting data to the CAN bus and listening to the data traffic on the CAN bus simultaneously is essential  
to support the bit-to-bit arbitration within CAN.  
ISO 11898-2:2016 specifies the voltage levels for HS CAN transceivers. Whether a data bit is dominant or  
recessive depends on the voltage difference between the CANH and CANL pins (VDiff = VCANH - VCANL).  
To transmit a dominant signal to the CAN bus the amplitude of the differential signal VDiff is higher than or  
equal to 1.5 V. To receive a recessive signal from the CAN bus the amplitude of the differential VDiff is lower than  
or equal to 0.5 V.  
In partially-supplied high speed CAN network, the bus nodes of one common network have different power  
supply conditions. Some nodes are connected to the power supply, while other nodes are disconnected from  
the power supply and in power-down state. Regardless of whether the CAN bus subscriber is supplied or not,  
each subscriber connected to the common bus media must not interfere with the communication. The  
TLE9350BSJ is designed to support partially-supplied networks. In power-down state, the receiver input  
resistors are switched off and the transceiver input has a high resistance.  
For permanently supplied ECUs, the HS CAN transceiver TLE9350BSJ provides a power-save mode. In power-  
save mode, the power consumption of the TLE9350BSJ is optimized to a minimum  
The voltage level on the digital input TxD and the digital output RxD is determined by the power supply level  
at the VCC pin. Depending on the voltage level at the VCC pin, the signal levels on the logic pins (STB, TxD and  
RxD) are compatible with microcontrollers having a 5 V I/O supply.  
Datasheet  
10  
Rev. 1.0  
2023-08-11  

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