Not Recommended For New Designs
THS1215
www.ti.com
SLAS292A–MARCH 2001–REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (AVDD = DVDD = 3.3 V, fs = 15 MHz/50% duty cycle, MODE = 1, 1-V input span,
internal reference, Tmin to Tmax) (unless otherwise noted)
DIGITAL INPUTS AND OUTPUTS (all supplies = 3.3 V)
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
DIGITAL INPUTS
All other inputs
CLK
0.8 × DVDD
0.8 × AVDD
VIH
VIL
High level input voltage
Low level input voltage
V
All other inputs
CLK
0.2 × DVDD
0.2 × AVDD
IIH
IIL
Ci
High level input current
Low level input current
Input capacitance
1
µA
pF
–1
5
DIGITAL OUTPUTS
VOH
VOL
High level output voltage
Low level output voltage
Iload = 50 µA
DVDD–0.4
V
V
Iload = –50 µA
0.4
High impedance output current
Rise/fall time
±1
µA
ns
tr/tf
CL = 10 pF
4.5
ANALOG INPUTS
Ci
Switched input capacitance
6
2
pF
ns
ns
µA
td(ap)
Aperture delay time
Aperture uncertainty (jitter)
DC leakage current (input = ±FS)
2
10
POWER SUPPLY (CLK = 15 MHz)
XVDD
IDD
Supply voltage (all supplies)
Supply current active - total
Supply current active - analog
Supply current active - digital
Standby supply current
3
3.3
45
34
11
3.6
V
53.5
mA
mA
mA
µA
µs
I(analog)
I(digital)
II(standby)
CLK = 0 MHz
1 µF bypass(1)
10 µF bypass(1)
1 µF bypass(2)
10
770
6.2
t(PU)
Power-up time for references from standby
Power-up time for valid ADC conversion
ms
ns
t(PUconv)
820
Clock = 15 MHz,
AIN+ and AIN– at Common
Mode or 1.65 V dc
148
167
177
36
PD
Power dissipation
mW
Clock = 15 MHz,
fin = 3.58 MHz at –1 dBFS
PD(STBY)
PSRR
Standby power dissipation
Power supply rejection ratio
CLK = 0 MHz
µW
±0.1
%FS
(1) Time for reference to recover to 1% of its final voltage level.
(2) Time for ADC conversions to be accurate to within 0.1% of fullscale.
5