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TDA7559 PDF预览

TDA7559

更新时间: 2024-02-19 06:46:04
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 商用集成电路
页数 文件大小 规格书
26页 179K
描述
TDA7559, TQFP-100

TDA7559 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:TQFP-100Reach Compliance Code:not_compliant
风险等级:5.92商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:S-PQFP-G100JESD-609代码:e0
端子数量:100最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP100,.63SQ,20
封装形状:SQUARE封装形式:FLATPACK
电源:3.3,5 V认证状态:Not Qualified
子类别:Other Consumer ICs表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
Base Number Matches:1

TDA7559 数据手册

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TDA7559  
PIN DESCRIPTION  
(continued)  
Reset  
Status (1)  
N.  
Name  
Type  
Function  
4
RESET  
I/O  
I
System Reset. A logic low level applied to RESET input initializes the  
microcontroller. The micro is responsible for initializing the DSPs. If the  
watchdog timer overflow occurs this pin is driven low for 1 watchdog  
timer cycle. During Debug Mode if this pin is pulled low in while the  
DBRQN line is pulled low then the DSP pointed to by the DBSEL pin will  
be reset.  
96  
97  
RXD(P3.0)  
TXD(P3.1)  
I/O  
I/O  
I
I
Microcontroller Standard Serial Interface (Asynchronous) Input Data. Or  
GPIO. This pin can also act as GPIO using the P3 and P3DIR registers.  
Microcontroller Standard Serial Interface (Asynchronous) Output Data.  
Or GPIO. This pin can also act as GPIO using the P3 and P3DIR  
registers.  
99  
98  
INT0(P3.2)  
INT1(P3.3)  
I/O  
I/O  
I
I
Microcontroller Interrupt 0. When pulled low, INT0 asserts a  
microcontroller external interrupt. In addition, if this pin is pulled low  
during powerdown this allows the M8051 to resume executing intructions  
where it left off. This pin can also act as GPIO using the P3 and P3DIR  
registers.  
Microcontroller Interrupt 1. When pulled low, INT1 asserts a  
microcontroller external interrupt. In addition, if this pin is pulled low  
during powerdown this allows the M8051 to resume executing intructions  
where it left off. This pin can also act as GPIO using the P3 and P3DIR  
registers.  
100  
1
T0(P3.4)  
T1(P3.5)  
I/O  
I/O  
I/O  
I
I
I
Microcontroller Timer 0 External Input. Input event clock for timer 0, or  
GPIO. This pin can also act as GPIO using the P3 and P3DIR registers.  
Microcontroller Timer 1 External Input. Input event clock for timer 1, or  
GPIO. This pin can also act as GPIO using the P3 and P3DIR registers.  
87  
GPIO0(P1.0)  
Microcontroller General Purpose. This GPIO line can be configured to be  
digital input or output by writing to the P1 and P1DIR registers.This pin is  
tri-stated while the RESET pin is held low and is pulled low when RESET  
is released. This pin will be pulled high when in IDLE or PWRDN modes.  
88  
89  
92  
93  
94  
95  
7
GPIO1(P1.1)  
GPIO2(P1.2)  
GPIO3(P1.3)  
GPIO4(P1.4)  
GPIO5(P1.5)  
GPIO6(P1.6)  
SCLK  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I
I
I
I
I
I
I
Microcontroller General Purpose. This GPIO line can be configured to be  
digital input or output by writing to the P1 and P1DIR registers. At reset it  
is configured as an input with the output tri-stated.  
Microcontroller General Purpose. This GPIO line can be configured to be  
digital input or output by writing to the P1 and P1DIR registers. At reset it  
is configured as an input with the output tri-stated.  
Microcontroller General Purpose. This GPIO line can be configured to be  
digital input or output by writing to the P1 and P1DIR registers. At reset it  
is configured as an input with the output tri-stated.  
Microcontroller General Purpose. This GPIO line can be configured to be  
digital input or output by writing to the P1 and P1DIR registers. At reset it  
is configured as an input with the output tri-stated.  
Microcontroller General Purpose. This GPIO line can be configured to be  
digital input or output by writing to the P1 and P1DIR registers. At reset it  
is configured as an input with the output tri-stated.  
Microcontroller General Purpose. This GPIO line can be configured to be  
digital input or output by writing to the P1 and P1DIR registers. At reset it  
is configured as an input with the output tri-stated.  
Microcontroller General Purpose. Each of the six GPIO lines can be  
individually configured to be digital input or output by writing to the P1  
and P1DIR registers. All GPIOs are configured to be inputs with the  
outputs tri-stated except for P1.0. This pin is tri-stated during while the  
RESET pin is held low and is pulled low when RESET is released. This  
pin will be pulled high when in IDLE or PWRDN modes.  
6
MOSI  
I/O  
I
Microcontroller SPI Master Output Slave Input Serial Data . Serial Data  
Output for SPI type serial port when in SPI Master Mode and Serial Data  
Input when in SPI Slave Mode.  
6/26  

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