Datasheet > TC9208M

TC9208M

更新时间： 2024-01-03 12:47:33

品牌	Logo	应用领域
其他 - ETC		以太网局域网（LAN）标准
页数	文件大小	规格书
53页	1807K
描述
8-Port 10/100/1000 Smart Ethernet Switch

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技术参数
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TC9208M 技术参数

生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	SDIP, SDIP28,.4	针数：	28
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.84	模拟集成电路 - 其他类型：	ANALOG CIRCUIT
JESD-30 代码：	R-PDIP-T28	JESD-609代码：	e0
长度：	25.6 mm	标称负供电电压 (Vsup)：	-15 V
信道数量：	6	功能数量：	1
端子数量：	28	最大通态电阻 (Ron)：	100 Ω
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SDIP
封装等效代码：	SDIP28,.4	封装形状：	RECTANGULAR
封装形式：	IN-LINE, SHRINK PITCH	电源：	+-15 V
认证状态：	Not Qualified	座面最大高度：	4.1 mm
最大信号电流：	0.0001 A	子类别：	Multiplexer or Switches
最大供电电流 (Isup)：	1 mA	最大供电电压 (Vsup)：	34 V
最小供电电压 (Vsup)：	16 V	标称供电电压 (Vsup)：	15 V
表面贴装：	NO	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	TIN LEAD
端子形式：	THROUGH-HOLE	端子节距：	1.778 mm
端子位置：	DUAL	宽度：	10.16 mm
Base Number Matches：	1

TC9208M 数据手册

TC9208M

Preliminary Data Sheet

8-Port 10/100/1000 Smart Ethernet Switch

This feature allows improved support for

Features

multimedia applications.

ꢀ

Stand Alone Switch On A Chip

The chip embeds IEEE 802.3 MAC functions for

each port and these functions support full and half

duplex modes for both 10 and 100 Mbits/s data

rates and full duplex for 1000 Mbit/s. Each port

includes dedicated receive and transmit FIFOs

with necessary logic to implement flow control for

both full and half duplex modes. TC9208M uses

IEEE 802.3x frame based flow control for full

duplex and backpressure for half duplex.

8 Ethernet 10/100/1000 ports

MII/GMII interface for all ports

Trunk group support

Four Classes of Service (CoS) selectable for

each port and/or checked via IP Header and

802.1Q VLAN Tag

ꢀ

Eight port-based VLANs

Maximum throughput, non head-of-line

blocking architecture

ꢀ

Embedded SSRAM packet buffer/address table

8K MAC address table

TC9208M handles an 8K address-lookup table

with searching, self-learning, and automatic aging,

at very high speed and excellent address space

coverage. Forwarding rules are implemented

according to IEEE 802.1D specifications. Filtering

capabilities for bad packets and packets with

Reserved Group Address DA are also provided.

Each port is configurable to 10 full/half duplex,

100 full/half duplex and 1000 full duplex mode

Flow-control ability is able to set for both full

and half duplex mode

ꢀ

Broadcast throttling

Port Mirroring

Serial EEPROM Interface, EEPROM is optional

MDIO master for PHY configuration / polling

0.18 micron technology

Increased interconnection bandwidth can be

achieved by using TC9208M’s trunking

capabilities. Several load-balancing schemes are

provided through pin and EEPROM configuration.

A port mirror feature, which it includes bad frames

optionally, can be used for debugging network

problems.

2V and 3.3V dual voltage power supply

Packaged in PBGA 292

27 MHz crystal input only

General Description

The pin configuration interface comprises 40

configurations, which are shared with GMII output

pins by latching the configuration data during

reset. An external EEPROM device can also be

used to configure the TC9208M at power-up. With

reference to pin configuration interface, the

EEPROM extends the chip’s configuration

capability with new features and enables a

jumper-less configuration mode using a parallel

interface for reprogramming. A virtual internal

EEPROM mode is also provided to enable the

use of the programming interface in the absence

of external EEPROM. TC9208M can make

effective use by most of its features using only the

pin configuration interface.

TC9208M is a fully integrated 8 port 10/100/1000

smart Ethernet switch controller designed for low

cost and high performance solutions. The chip

embeds necessary SSRAM for packet buffering

and MAC address table. It provides MII / GMII

interface for all ports.

A store-and-forward switching method using a

non-blocking architecture is implemented within

TC9208M to improve the availability and

bandwidth. The chip embeds packet buffer, which

it supports normal and priority queues for each

transmission port.

TC9208M provides evolved CoS with four levels

of priority. The priority can be checked via layer 2

(802.1Q VLAN Tagging) and/or layer 3 (IP Header

TOS bits) packets. Port based priority is also

provided to ensure transmission with precedence

for all packets incoming from selected port(s).

TC9208M includes a physical layer configuration /

polling entity, which it is use to configure the phy

functions and to monitor the physical layer

transceiver’s speed, duplex mode, link status and

full duplex flow control ability for each port. The

chip provides four modes for phy configurations,

Confidential.

1/53

August 1, 2003

TC9208M-DS-R06

12 3 4 5 6 7...53

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