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TAS3202PAGR

更新时间： 2024-02-01 11:04:19
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
66页 802K
描述
AUDIO DSP WITH ANALOG INTERFACE

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中文翻译

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TAS3202PAGR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Not Recommended零件包装代码：QFP
包装说明：TFQFP, TQFP64,.47SQ针数：64
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：8 weeks风险等级：5.3
商用集成电路类型：CONSUMER CIRCUITJESD-30 代码：S-PQFP-G64
JESD-609代码：e4长度：10 mm
湿度敏感等级：4功能数量：1
端子数量：64最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：TFQFP封装等效代码：TQFP64,.47SQ
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Other Consumer ICs最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：10 mmBase Number Matches：1

TAS3202PAGR 数据手册

 浏览型号TAS3202PAGR的Datasheet PDF文件第5页浏览型号TAS3202PAGR的Datasheet PDF文件第6页浏览型号TAS3202PAGR的Datasheet PDF文件第7页浏览型号TAS3202PAGR的Datasheet PDF文件第9页浏览型号TAS3202PAGR的Datasheet PDF文件第10页浏览型号TAS3202PAGR的Datasheet PDF文件第11页 
TAS3202  
SLES208B–JUNE 2009–REVISED MARCH 2011  
www.ti.com  
3.2 Terminal Descriptions  
TERMINAL  
INPUT/  
PULLUP/  
DESCRIPTION  
Analog input, channel 1, left, – input  
OUTPUT(1)  
PULLDOWN(2)  
NAME  
NO.  
13  
12  
15  
14  
17  
16  
19  
18  
33  
34  
35  
36  
AIN1LM  
AIN1LP  
Analog input  
Analog input  
Analog input  
Analog input  
Analog input  
Analog input  
Analog input  
Analog input  
Analog output  
Analog output  
Analog output  
Analog output  
Pull to VMID(3)  
Pull to VMID(3)  
Pull to VMID(3)  
Pull to VMID(3)  
Analog input, channel 1, left, + input  
Analog input, channel 1, right, – input  
Analog input, channel 1, right, + input  
Analog input, channel 2, left, – input  
Analog input, channel 2, left, + input  
Analog input, channel 2, right, – input  
Analog input, channel 2, right, + input  
Analog output, channel 1, left, – output  
Analog output, channel 1, left, + output  
Analog output, channel 1, right, – output  
Analog output, channel 1, right, + output  
AIN1RM  
AIN1RP  
AIN2LM  
AIN2LP  
AIN2RM  
AIN2RP  
AOUTLM  
AOUTLP  
AOUTRM  
AOUTRP  
3.3-V analog power supply. This pin must be decoupled according to  
good design practices.  
AVDD1  
AVSS1  
AVDD2  
AVSS2  
AVDD3  
24  
11  
28  
37  
40  
Power  
Power  
Power  
Power  
Power  
Analog supply ground  
3.3-V analog power supply. This pin must be decoupled according to  
good design practices.  
Analog supply ground  
3.3-V analog power supply. This pin must be decoupled according to  
good design practices.  
AVSS3  
CS0  
38  
6
Power  
Analog supply ground  
I2C Chip select  
Digital input  
3.3-V digital power supply. This pin must be decoupled according to  
good design practices.  
DVDD1  
DVSS1  
DVDD2  
DVSS2  
DVDD3  
9
Power  
Power  
Power  
Power  
Power  
8
Digital supply ground  
3.3-V digital power supply. This pin must be decoupled according to  
good design practices.  
45  
44  
57  
Digital supply ground  
3.3-V digital power supply. This pin must be decoupled according to  
good design practices.  
DVSS3  
GPIO1  
GPIO2  
56  
4
Power  
Digital supply ground  
Digital I/O  
Digital I/O  
General-purpose input/output  
General-purpose input/output  
3
Slave I2C serial clock input/output. Normally connected to the system  
microprocessor.  
I2C1_SCL  
1
Digital I/O  
Slave I2C serial control data interface input/output. Normally connected  
to system micro.  
Master I2C serial clock output. Normally connected to EEPROM.  
Master I2C serial control data interface input/output. Normally  
connected to EEPROM.  
I2C1_SDA  
I2C2_SCL  
I2C2_SDA  
2
Digital I/O  
Digital output  
Digital I/O  
64  
63  
LRCLK_IN  
58  
51  
Digital input  
Pulldown  
Pulldown  
Serial data input left/right clock for I2S interface  
Serial data output left/right clock for I2S interface  
LRCLK_OUT  
Digital output  
MCLK input is used in slave mode. MCLK_IN must be locked to  
LRCLK_IN, and the frequency is 512Fs (24.576 MHz for 48-kHz Fs).  
MCLK_IN  
43  
48  
Digital input  
MCLK_OUT1  
Digital output  
12.288-MHz clock output. This output is valid even when reset is LOW.  
(1) I = input; O = output  
(2) All pullups are 20-μA weak pullups, and all pulldowns are 20-μA weak pulldowns. The pullups and pulldowns are included to ensure  
proper input logic levels if the terminals are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input). Devices that drive  
inputs with pullups must be able to sink 20 μA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be  
able to source 20 μA while maintaining a logic-1 drive level.  
(3) Pull to VMID when analog input is in single-ended mode.  
8
Physical Characteristics  
Copyright © 2009–2011, Texas Instruments Incorporated  
Submit Documentation Feedback  
Product Folder Link(s): TAS3202  
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