T4260
7. Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VST/VSPLL = +8.5V, Tamb = +25°C
No.
13
Parameters
IF Gain
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
12 dB
14 dB
16 dB
18 dB
20 dB
22 dB
24 dB
26 dB
28 dB
30 dB
32 dB
34 dB
36 dB
38 dB
40 dB
42 dB
9
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
A(1)
A(1)
A(1)
C(1)
A(1)
C(1)
C(1)
C(1)
A(1)
C(1)
C(1)
C(1)
C(1)
C(1)
C(1)
A(1)
12
14
17
17
19
21
23
25
27
29
31
33
35
37
39
IF gain
13.1 (programmable with bit 6
- bit 9)
14
SWO1 (Open Drain)
14.1 Output voltage LOW
13
13
13
VSWOL
IOHL
100
160
200
10
mV
µA
V
A
A
C
I = 1 mA,
VSWO1 = 8.5V
Output leakage current
HIGH
14.2
14.3 Maximum output voltage
8.5
15
SW2/AGC (Open Drain in Switch Mode)
15.1 Output voltage LOW
11
11
11
VSWOL
IOHL
100
160
200
10
mV
µA
V
A
A
C
I = 1 mA,
V11 = 6 V
15.2 Output leakage current
HIGH
15.3 Maximum output voltage
6
16
3-wire Bus, ENABLE, DATA, CLOCK
High
Low
VBUS
VBUS
2.7
-0.3
5.3
+0.8
V
V
A
A
16.1 Input voltage
16.2 Clock frequency
16.3 Period of CLK
23-25
24
1.0
MHz
B
tH
tL
250
250
ns
ns
C
C
24
16.4 Rise time EN, DATA,
CLK
23-25
tR
400
100
ns
C
16.5 Fall time EN, DATA, CLK
16.6 Set-up time
23-25
23-25
23
tF
ns
ns
ns
ns
C
C
C
C
tS
100
250
0
16.7 Hold time EN
tHEN
tHDA
16.8 Hold time DATA
25
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. Minimum and maximum limits are characterized for entire temperature range (–40°C to +85°C) but are tested at +25°C
9
4528M–AUDR–03/08