HM25Q128A
8.5. AC Electrical Characteristics
Table 8.6 AC Electrical Characteristics
SPEC
SYMBOL
ALT
Parameter
UNIT
MIN
D.C.
TYP
MAX
Clock frequency for all QPI/Quad IO instructions with
HFQ, Vcc=2.7V-3.6V
Clock frequency for all SPI instructions (except 03h/EBh)
Vcc=2.7V-3.6V
Clock frequency for all SPI instructions (except 03h/EBh)
Vcc=2.3V-2.7V(1)
104
104
80
MHz
MHz
MHz
FR
FR
fC
fC
fC
D.C.
D.C.
FR
fR
Clock frequency for Read Data instruction (03h)
D.C.
4
60
MHz
ns
Clock High, Low Time for all instructions except Read
Data (03h)
(2)
tCLH, tCLL
(2)
Clock High, Low Time for Read Data (03h) instruction
tCRLH, tCRLL
6
0.1
0.1
ns
V/ns
V/ns
(3)
tCLCH
Clock Rise Time peak to peak
Clock Fall Time peak to peak
(3)
tCHCL
CS# Active Setup Time relative to CLK
CS# Not Active Hold Time relative to CLK
tSLCH
tCSS
5
ns
tCHSL
tDVCH
tCHDX
5
2
5
ns
ns
ns
tDSU
tDH
Data In Setup Time
Data In Hold Time
CS# Active Hold Time relative to CLK
tCHSH
5
ns
CS# Not Active Setup Time relative to CLK
tSHCH
tSHSL1
5
10
ns
ns
tCSH1
tCSH2
CS# Deselect Time SPI (Array ReadArray Read)
CS# Deselect Time for Erase/ProgramRead SR
Volatile Status Register Write Time
tSHSL2
50
ns
CS# Deselect Time for non Array Read→Array
Read(Dual IO, Quad IO and QPI Read)
Output Disable Time
tSHSL3
tCSH3
tDIS
tV
ns
ns
ns
100
(3)
tSHQZ
7
7
9
Clock Low to Output Valid 2.7V- 3.6V
tCLQV
Clock Low to Output Valid 2.3V- 2.7
Output Hold Time
V
tCLQV
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
tHHQX
tHLQZ
tV
tHO
ns
ns
ns
ns
ns
ns
ns
ns
2
5
5
5
5
HOLD# Active Setup Time relative to CLK
HOLD# Active Hold Time relative to CLK
HOLD# Not Active Setup Time relative to CLK
HOLD# Not Active Hold Time relative to CLK
HOLD# to Output Low-Z
(3)
tLZ
7
12
(3)
tHZ
HOLD# to Output High-Z
(4)
Write Protect Setup Time Before CS# Low
Write Protect Hold Time After CS# High
CS# High to Power-down Mode
tWHSL
20
ns
ns
μs
(4)
tSHWL
100
(3)
3
8
tDP
CS# High to Standby Mode without Electronic Signature
Read
CS# High to Standby Mode with Electronic Signature
Read
CS# High to next Command after Suspend
Write Status Register Time
(3)
tRES1
μs
μs
(3)
tRES2
6
(3)
tsus
tW
20
100
μs
ms
10
Page Program Time
0.5
1.5
tPP
ms
Sector Erase Time (4KB)
35
200
tSE
tBE1
tBE2
tCE
ms
s
s
s
ns
μs
Block Erase Time (32KB)
Block Erase Time (64KB)
Chip Erase Time
End of Reset Instruction to CE# High
CE# High to next Instruction after Reset
0.8
2
200
0.15
0.25
50
(3)
tRCH
40
10
(3)(5)
tRST
Notes:
(1)With HFQ, the clock frequency of all SPI instructions(except 03h/EBh) can reach 104MHz.
(2)Clock high + Clock low must be less than or equal to 1/fC.
(3)Value guaranteed by design and/or characterization, not 100% tested in production.
(4)Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set to 1.4. For multiple
bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number of bytes
programmed.
(5)It’s possible to reset the device with shorter tRESET (as short as a few hundred ns), a 1us minimum is recommended to
ensure reliable operation.
69
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