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SY89420

更新时间: 2024-09-29 22:42:35
品牌 Logo 应用领域
麦瑞 - MICREL /
页数 文件大小 规格书
8页 94K
描述
5V/3.3V DUAL PHASE LOCKED LOOP

SY89420 数据手册

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5V/3.3V DUAL  
PHASE LOCKED LOOP  
ClockWorks™  
SY89420V  
FEATURES  
DESCRIPTION  
3.3V and 5V power supply options  
1.12GHz maximum VCO frequency  
The SY89420V device consists of two identical, low  
jitter, digitalPhaseLockedLoopsbasedonMicrel-Synergy's  
differential PLL technology. Each of the PLLs (PLLA and  
PLLB) is capable of operating in the 30MHz to 560MHz  
input reference frequency range independently of the other  
and is configurable separately. The PLLs can be configured  
to be matched in all regards, or can be configured so that  
PLLB is used as a frequency doubler, while PLLA is used  
to regenerate the undoubled frequency.  
Two reference inputs (RINX and RINX), two feedback  
inputs (FINX and FINX), two filter pins (F1X and F2X) and  
two differential outputs (FOUTX and FOUTX) are provided  
for each of the two PLLs. The reference and feedback  
inputs can be used as either differential or single-ended  
inputs. In single-ended mode RINX and FINX can be  
connected to either VBB for normal 100K PECL levels or  
VTH for normal TTL levels.  
30MHz to 560MHz reference input operating  
frequency  
Frequency doubler mode  
Low jitter design  
PECL differential outputs  
PECL and TTL reference voltages available  
External loop filter optimizes performance/cost  
Available in 28-pin PLCC package  
APPLICATIONS  
Workstations  
Feedback for the loops is realized by connecting FOUTX,  
FOUTX to FINX, FINX by means of external circuitry. This  
allows the user the flexibility of inserting additional circuitry  
off-chip in the feedback paths, such as a divider. Pulldown  
resistors are required for the FOUTX and FOUTX pins.  
Use of a phase-frequency detector results in excellent  
PLL locking and tracking characteristics. Error correction  
voltages are generated by the detector if either phase or  
frequency deviations occur. The VCO has a frequency  
range covering more than a 2:1 ratio from 480MHz to  
1120MHz.  
Advanced communications  
High-end consumer  
High-performance computing  
PIN CONFIGURATION  
Select pins S1X and S2X are used to program the N  
dividers for optimum VCO operation, in other words with  
the VCO in the center of its range. Additional select pins,  
S3B and S4B, are provided for PLLB. When both S3B and  
S4B are low, PLLB is identical to PLLA. When S3B is high,  
NB can be set to 1, 10, 18, or 20. When S4B is high, the  
frequency doubler option is enabled (P = 2). All Select pins  
are TTL compatible.  
24 23 22 21 20 19  
25  
26  
V
CCOB  
18  
17  
16  
15  
14  
S4B  
FOUTB  
FOUTB  
27  
28  
1
RINB  
RINB  
TOP VIEW  
PLCC  
V
CC  
V
EE  
J28-1  
FOUTA  
FOUTA  
RINA  
RINA  
2
3
13  
12  
V
CCOA  
VBB  
4
5
6
7
8
9
10 11  
Rev.: K  
Amendment: /0  
Issue Date: May 2000  
1

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