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SY89425

更新时间： 2024-09-29 22:42:35

品牌	Logo	应用领域
麦瑞 - MICREL		时钟
页数	文件大小	规格书
8页	96K
描述
DUAL SONET OC-12 CLOCK SYNTHESIZER

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数据手册

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SY89425 数据手册

DUAL SONET OC-12

CLOCK SYNTHESIZER

ClockWorks™

SY89425

DESCRIPTION

FEATURES

■ Two independently-powered 622.08MHz clock

Micrel-Synergy's SY89425 Dual Phase Locked Loop

(PLL) consists of two totally separate, SONET compliant

622.08MHz clock generators on one chip. The user may

select to power both PLLs or PLL A only. Each PLL

produces a low-jitter OC-12/STS-12 clock rate from an

input reference clock of 38.88, 51.84, or 77.76MHz. When

using both PLLs, it is not necessary that they share a

common reference clock (e.g., PLL A may operate from an

STS-1 reference of 51.84MHz, while PLL B operates from

an OC-3/STS-3 reference of 77.76MHz).

The SY89425 operates from a single +5 volt supply, and

requires only a simple series RC loop filter for each PLL.

Coupling Micrel-Synergy's advanced PLL technology

with our proprietary ASSET™ bipolar process has produced

a clock generator IC which exceeds applicable Bellcore

and ANSI specifications, while setting a new standard for

performance and flexibility.

sources one chip

■ Differential PECL outputs

■ TTL/CMOS compatible inputs

■ SONET compliant jitter performance (≤0.01UI)

■ Choice of three reference frequencies for each PLL

■ Only 395mW per PLL (typ)

■ Complies with Bellcore, CCITT and ANSI standards

■ Single +5 volt power supply

■ Fully compatible with industry standard 10KH I/O

levels

■ Available in 28-pin PLCC package

TYPICAL APPLICATION

PIN CONFIGURATION

+5V

25 24 23 22 21 20 19

GND

VCCA

VCCOA

CK622AP

CK622AN

VCCOA

SEL39A

SEL78A

RSTA

RFCKA

(TTL)

CLOCK IN

0.1uF

RFCKA

VCCA

PLCC

TOP VIEW

GND

FLTRAN

FLTRAP

RFCKB

VCCOB

PLL A

CK622AP

(PECL)

622.08MHz

SEL78B

SEL39B

CK622BN

CK622BP

500Ω

CK622AN

SEL39A

(TTL)

10 11

2X 50Ω

SEL78A

(TTL)

+3V

PLL B

GND

AGND

(SAME AS PLL A)

Rev.: E

Amendment: /0

Issue Date: August, 1998

12 3 4 5 6 7 8

中文翻译

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