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SY89313VMG-TR PDF预览

SY89313VMG-TR

更新时间: 2024-09-30 15:53:19
品牌 Logo 应用领域
美国微芯 - MICROCHIP 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
6页 53K
描述
89313 SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8

SY89313VMG-TR 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:HVSON,Reach Compliance Code:compliant
HTS代码:8542.39.00.01Factory Lead Time:9 weeks
风险等级:2.28其他特性:IT ALSO REQUIRES 5V SUPPLY
系列:89313输入调节:DIFFERENTIAL
JESD-30 代码:S-PDSO-N8JESD-609代码:e4
长度:2 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:8
实输出次数:2最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HVSON封装形状:SQUARE
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
传播延迟(tpd):0.46 ns座面最大高度:0.9754 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:2 mm最小 fmax:4000 MHz
Base Number Matches:1

SY89313VMG-TR 数据手册

 浏览型号SY89313VMG-TR的Datasheet PDF文件第2页浏览型号SY89313VMG-TR的Datasheet PDF文件第3页浏览型号SY89313VMG-TR的Datasheet PDF文件第4页浏览型号SY89313VMG-TR的Datasheet PDF文件第5页浏览型号SY89313VMG-TR的Datasheet PDF文件第6页 
®  
®
3.3V/5V, 4GHz PECL/ECL  
Precision Edge  
÷ 4 CLOCK GENERATOR  
SY89313V  
FEATURES  
Guaranteed AC performance over temperature and  
®
Precision Edge  
voltage  
• > 4GHz f  
input frequency  
MAX  
DESCRIPTION  
• < 240ps t /t  
r f  
• < 500ps T  
PD  
The SY89313V is a differential ECL/PECL integrated ÷4  
3.3V and 5V power supply operation  
100k ECL/PECL compatible I/O  
divider clock generator. It is functionally equivalent to the  
®
SY100EP33V but in an ultra-small 8-lead MLF package  
Wide operating temperature range: –40°C to +85°C  
that features a 70% smaller footprint.  
®
Available in ultra-small 8-pin MLF (2mm × 2mm)  
The V pin, an internally generated voltage supply, is  
BB  
package  
available for this device only. For single-ended input  
conditions, the unused differential input is connected to V  
BB  
as a switching reference voltage. V may also re-bias AC-  
BB  
coupled inputs. When used, decouple V and V  
via a  
BB  
CC  
0.01µF capacitor and limit current sourcing or sinking to  
0.5mA. When not used, V should be left open.  
BB  
The reset pin is asynchronous and is asserted on the  
rising edge. Upon power-up, the internal flip-flops will be in  
a random state; the reset allows for the synchronous use of  
multiple SY89313V’s in a system.  
(1)  
PIN CONFIGURATION/BLOCK DIAGRAM  
TRUTH TABLE  
CLK  
/CLK  
RESET  
Q
L
/Q  
H
RESET  
CLK  
1
2
3
4
8
VCC  
Q
X
X
Z
L
R
7
6
5
F
F
÷ 4  
Note:  
1.  
/CLK  
VBB  
/Q  
= LOW-to-HIGH transition  
= HIGH-to-LOW transition  
F = Divide by 4 function  
VEE  
TOP VIEW  
8-Pin MLF®  
Ultra-Small Outline (2mm x 2mm)  
Precision Edge is a trademark of Micrel, Inc.  
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.  
Rev.: C  
Amendment: /0  
M9999-051006  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: May 2006  

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