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SY89321LMITR

更新时间: 2024-11-26 22:10:03
品牌 Logo 应用领域
麦瑞 - MICREL /
页数 文件大小 规格书
5页 40K
描述
3.3V DIFFERENTIAL LVPECL-to-LVTTL TRANSLATOR

SY89321LMITR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DFN包装说明:HVSON, SOLCC8,.08,20
针数:8Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.41最大延迟:2.5 ns
接口集成电路类型:PECL TO TTL TRANSLATORJESD-30 代码:S-XDSO-N8
JESD-609代码:e0长度:2 mm
湿度敏感等级:2位数:1
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
输出锁存器或寄存器:NONE输出极性:TRUE
封装主体材料:UNSPECIFIED封装代码:HVSON
封装等效代码:SOLCC8,.08,20封装形状:SQUARE
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):240
电源:3.3 V认证状态:Not Qualified
座面最大高度:0.9754 mm子类别:Level Translators
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:ECL100K温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn80Pb20)端子形式:NO LEAD
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:2 mm

SY89321LMITR 数据手册

 浏览型号SY89321LMITR的Datasheet PDF文件第2页浏览型号SY89321LMITR的Datasheet PDF文件第3页浏览型号SY89321LMITR的Datasheet PDF文件第4页浏览型号SY89321LMITR的Datasheet PDF文件第5页 
3.3V DIFFERENTIAL  
LVPECL-to-LVTTL  
TRANSLATOR  
Precision Edge™  
SY89321L  
FEATURES  
3.3V power supply  
Precision Edge™  
1.9ns typical propagation delay  
275MHz f  
(clock bit stream, not pseudo-random)  
MAX  
DESCRIPTION  
Differential LVPECL inputs  
24mA LVTTL outputs  
Flow-through pinouts  
The SY89321L is a differential LVPECL-to-LVTTL  
translator requiring only a single +3.3V power. Because  
LVPECL (Low Voltage Positive ECL) levels are used, only  
+3.3V and ground are required. The SY89321L is functionally  
equivalent to the SY100EPT21L, but in an ultra-small  
8-lead MLF™ package that features a 70% smaller footprint.  
This ultra-small package and low skew single gate design  
make the SY89321L ideal for applications that require the  
translation of a clock or data signal where minimal space,  
low power and low cost are critical.  
Internal input resistors: pulldown on IN, pulldown  
and pullup on /IN  
Q output will default LOW with inputs open  
V output  
BB  
Available in ultra-small 8-pin MLF™ (2mm x 2mm)  
package  
V
allows a differential, single-ended, or AC-coupled  
BB  
interface to the device. If used, the V output should be  
BB  
bypassed to V  
with 0.01µF capacitor.  
CC  
Under open input conditions, the /IN will be biased at  
BLOCK DIAGRAM  
a V /2 voltage level and the IN input will be pulled to  
CC  
ground. This condition will force the Q output low to  
provide added stability.  
The SY89321L is compatible with positive ECL 100k  
logic levels.  
IN  
LVPECL  
Q
LVTTL  
/IN  
Precision Edge is a trademark of Micrel, Inc.  
MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc.  
Rev.: A  
Amendment: /0  
1
Issue Date: August 2003  

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