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SY54020RMGTR PDF预览

SY54020RMGTR

更新时间： 2024-02-14 00:28:04
品牌 Logo 应用领域
麦瑞 - MICREL 逻辑集成电路驱动
页数 文件大小 规格书
14页 551K
描述
Low Voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with /EN and Fail-Safe Input 3.2Gbps

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SY54020RMGTR 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：HVQCCN,Reach Compliance Code：compliant
HTS代码：8542.39.00.01Factory Lead Time：14 weeks
风险等级：5.66系列：S
输入调节：DIFFERENTIAL LATCHEDJESD-30 代码：S-XQCC-N16
JESD-609代码：e4长度：3 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER湿度敏感等级：2
功能数量：1反相输出次数：
端子数量：16实输出次数：4
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：260传播延迟（tpd）：0.49 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.02 ns
座面最大高度：0.9 mm最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：3 mm
最小 fmax：2500 MHzBase Number Matches：1

SY54020RMGTR 数据手册

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SY54020R  
Low Voltage 1.2V/1.8V/2.5V CML 1:4 Fanout  
Buffer with /EN and Fail-Safe Input  
3.2Gbps, 2.5GHz  
General Description  
The SY54020R is a fully differential, low voltage  
1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with active-low  
Enable (/EN) and Fail-Safe Input (FSI). The Enable is  
synchronous so that the outputs will only be  
enabled/disabled when they are already in the LOW  
state. This avoids any chance of generating a runt clock  
pulse when the device is enabled/disabled as can  
happen with an asynchronous control. When this device  
is used as a clock fanout, disabling the downstream  
clock may reduce system power. FSI is a special circuit  
designed to sense the amplitude of the input signal and  
to latch the output when an invalid or no signal is  
present at the input. The SY54020R can process clock  
signals up to 2.5 GHz or data patterns up to 3.2Gbps.  
Precision Edge®  
Features  
• 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with FSI  
• Active-low Enable (/EN) input to disable the outputs  
• Guaranteed AC performance over temperature and  
voltage:  
– DC-to > 3.2Gbps Data throughput  
– DC-to > 2.5GHz Clock throughput  
– <400 ps propagation delay (IN-to-Q)  
– <20ps within-device skew  
– <100 ps rise/fall times  
• Ultra-low jitter design  
– <1psRMS cycle-to-cycle jitter  
The differential input includes Micrel’s unique, 3-pin  
input termination architecture that interfaces to LVPECL,  
LVDS or CML differential signals as small as 100mV  
(200mVpp) without any level-shifting or termination  
resistor networks in the signal path. For AC-coupled  
input interface applications, an internal voltage  
reference is provided to bias the VT pin. The outputs are  
CML, with extremely fast rise/fall times guaranteed to be  
less than 100ps.  
• High-speed CML outputs  
• 2.5V ±5% VCC , 1.2/1.8V/2.5V ±5% VCCO power supply  
operation  
• Industrial temperature range: –40°C to +85°C  
• Available in 16-pin (3mm x 3mm) MLF® package  
Applications  
The SY54020R operates from a 2.5V ±5% core supply  
and a 1.2V, 1.8V or 2.5V ±5% output supply and is  
guaranteed over the full industrial temperature range  
(–40°C to +85°C).  
• SONET clock and data distribution  
• Fibre Channel clock and data distribution  
• Gigabit Ethernet clock and data distribution  
Datasheets and support documentation can be found on  
Micrel’s web site at: www.micrel.com.  
Markets  
• Storage  
• ATE  
Functional Block Diagram  
• Test and measurement  
• Enterprise networking equipment  
• High-end servers  
• Access  
• Metro area network equipment  
Precision Edge is a registered trademark of Micrel, Inc.  
MLF and MicroLeadFrame are registered trademarks of Amkor Technology.  
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com  
M9999-041409-A  
hbwhelp@micrel.com or (408) 955-1690  
April 2009  
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