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SY10H841ZC PDF预览

SY10H841ZC

更新时间: 2024-09-29 22:07:31
品牌 Logo 应用领域
麦瑞 - MICREL 输出元件
页数 文件大小 规格书
6页 74K
描述
SINGLE SUPPLY QUAD PECL-TO-TTL W/LATCHED OUTPUT ENABLE

SY10H841ZC 数据手册

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ClockWorks™  
SY10H841  
SY100H841  
FINAL  
SINGLE SUPPLY QUAD  
PECL-TO-TTLW/LATCHED  
OUTPUT ENABLE  
FEATURES  
DESCRIPTION  
Translates positive ECL to TTL (PECL-to-TTL)  
300ps pin-to-pin skew  
The SY10/100H841 are single supply, low skew  
translating 1:4 clock drivers.  
The devices feature a 24mA TTL output stage, with  
AC performance specified into a 50pF load capacitance.  
A latch is provided on-chip. When LEN is LOW (or left  
open, in which case it is pulled low by the internal pull-  
downs) the latch is transparent. A HIGH on the enable  
pin (EN) forces all outputs LOW.  
500ps part-to-part skew  
Differential internal design for increased noise  
immunity and stable threshold inputs  
VBB reference output  
Single supply  
As frequencies increase to 40MHz and above, precise  
timing and shaping of clock signals becomes extremely  
important. The H841 solves several clock distribution  
problems such as minimizing skew (300ps), maximizing  
clock fanout (24mA drive), and precise duty cycle control  
through a proprietary differential internal design.  
The 10K version is compatible with 10KH ECL logic  
levels. The 100K version is compatible with 100K levels.  
Enable input  
Latch enable input  
Extra TTL and ECL power/ground pins to reduce  
cross-talk/noise  
High drive capability: 24mA each output  
Fully compatible with industry standard 10K, 100K  
I/O levels  
Available in 16-pin SOIC package  
PIN CONFIGURATION  
BLOCK DIAGRAM  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Q
3
LEN  
EN  
Q
Q
Q
Q
0
1
2
3
G
T
2
GE  
Q
VE  
SOIC  
Z16-1  
V
T
T
D
V
Q
G
Q
1
T
0
D
VBB  
GT  
V
BB  
D
D
D Q  
PIN NAMES  
LEN  
EN  
Pin  
GT  
Function  
TTL Ground (0V)  
VT  
TTL VCC (+5.0V)  
VE  
ECL VCC (+5.0V)  
GE  
ECL Ground (0V)  
D, D  
VBB  
Q0 - Q3  
EN  
Signal Input (PECL)  
VBB Reference Output (PECL)  
Signal Outputs (TTL)  
Enable Input (PECL)  
Latch Enable Input  
LEN  
Rev.: F  
Amendment:/0  
Issue Date: May, 1999  
1

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