SY10H842

更新时间： 2024-09-29 22:07:31

品牌	Logo	应用领域
麦瑞 - MICREL		输出元件
页数	文件大小	规格书
6页	83K
描述
SINGLE SUPPLY QUAD PECL-TO-TTL OUTPUT ENABLE

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中文翻译

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数据手册

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SY10H842 数据手册

SINGLE SUPPLY

QUAD PECL-TO-TTL

OUTPUT ENABLE

ClockWorks™

SY10H842

SY100H842

FEATURES

DESCRIPTION

■ Translates positive ECL-to-TTL (PECL-to-TTL)

■ 300ps pin-to-pin skew

The SY10/100H842 are single supply, low skew

translating 1:4 clock drivers.

The devices feature a 24mA TTL output stage, with

AC performance specified into a 50pF load capacitance.

A HIGH on the enable pin (EN) forces all outputs LOW.

As frequencies increase to 40MHz and above, precise

timing and shaping of clock signals becomes extremely

important. The H842 solves several clock distribution

problems such as minimizing skew 300ps), maximizing

clock fanout (24mA drive), and precise duty cycle control

through a proprietary differential internal design.

■ 500ps part-to-part skew

■ Differential internal design for increased noise

immunity and stable threshold inputs

■ VBB reference output

■ Single supply

■ Enable input

■ Extra TTL and ECL power/ground pins to reduce

cross-talk/noise

The 10K version is compatible with 10KH ECL logic

levels. The 100K version is compatible with 100K levels.

■ High drive capability: 24mA each output

■ Fully compatible with industry standard 10K, 100K

I/O levels

■ Available in 16-pin SOIC package

BLOCK DIAGRAM

PIN CONFIGURATION

TTL Outputs

SOIC

Z16-1

VBB

PIN NAMES

ECL Input

Function

TTL Ground (0V)

TTL VCC (+5.0V)

ECL VCC (+5.0V)

VBB

ECL Ground (0V)

D, D

VBB

Q0 - Q3

Signal Input (PECL)

VBB Reference Output (PECL)

Signal Outputs (TTL)

Enable Input (PECL)

Rev.: E

Amendment:/1

Issue Date: August, 1999

12 3 4 5 6

中文翻译

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