SY10H602JC

更新时间： 2024-09-29 22:07:31

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
4页	74K
描述
9-BIT LATCHED

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中文翻译

获取价格

数据手册
替代型号

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SY10H602JC 数据手册

9-BIT LATCHED

TTL-TO-ECL

SY10H602

SY100H602

DESCRIPTION

FEATURES

■ 9-bit ideal for byte-parity applications

■ Flow-through configuration

The SY10/100H602 are 9-bit, dual supply TTL-to-ECL

translators with latches. Devices in the Micrel-Synergy

9-bit translator series utilize the 28-lead PLCC for optimal

power pinning, signal flow-through and electrical

performance.

The H602 features D-type latches. Latching is

controlled by Latch Enable (LEN), while the Master Reset

input resets the latches. A post-latch logic enable is also

provided (ENECL), allowing control of the output state

without destroying latch data. All control inputs are ECL

level.

■ Extra TTL and ECL power/ground pins to minimize

switching noise

■ Dual supply

■ 3.5ns max. D to Q

■ PNP TTL inputs for low loading

■ Choice of ECL compatibility: MECL 10KH (10Hxxx)

or 100K (100Hxxx)

■ Fully compatible with Motorola MC10H/100H602

■ Available in 28-pin PLCC package

The 10H version is compatible with MECL 10KH ECL

logic levels. The 100H version is compatible with 100K

levels.

BLOCK DIAGRAM

PIN CONFIGURATION

ENECL

D Q

25 24 23 22 21 20 19

D Q

VCCE

VCCO

TOP VIEW

PLCC

GND

D Q

LEN

ENECL

VCCO

D Q

10 11

TTL

D Q

ECL

D Q

PIN NAMES

GND

Function

D Q

TTL Ground (0V)

VCCE

VCCO

VCCT

ECL VCC (0V)

D Q

ECL VCC (0V) — Outputs

TTL Supply (+5.0V)

ECL Supply (–5.2/–4.5V)

Data Inputs (TTL)

D Q

VEE

D0–D8

Q0–Q8

ENECL

LEN

Data Outputs (ECL)

Enable Control (ECL)

Latch Enable (ECL)

Master Reset (ECL)

Rev.: D

Amendment:/0

Issue Date: March, 1998

12 3 4

中文翻译

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SY10H602JC 替代型号

型号	品牌	替代类型	描述	数据表
SY10H602JZ	MICREL	功能相似	9-BIT LATCHED TTL-TO-ECL

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