Datasheet > SY10EL34_06

SY10EL34_06

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
麦瑞 - MICREL		时钟发生器
页数	文件大小	规格书
5页	61K
描述
5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP

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SY10EL34_06 数据手册

Precision Edge^®

SY10EL34/L

Precision Edge

Micrel, Inc.

SY1^S0^YE¹L⁰⁰3^E4^L/³L^4/L

SY100EL34/L

5V/3.3V ÷2, ÷4, ÷8 CLOCK

GENERATION CHIP

FEATURES

■ 3.3V and 5V power supply options

■ 50ps output-to-output skew

Precision Edge

■ Synchronous enable/disable

DESCRIPTION

■ Master Reset for synchronization

■ Internal 75KΩ input pull-down resistors

■ Available in 16-pin SOIC package

The SY10/100EL34/L are low skew ÷2, ÷4, ÷8 clock

generation chips designed explicitly for low skew clock

generation applications. The internal dividers are

synchronous to each other, therefore, the common output

edges are all precisely aligned. The devices can be driven

by either a differential or single-ended ECL or, if positive

power supplies are used, PECL input signal. In addition,

by using the VBB output, a sinusoidal source can be AC-

coupled into the device. If a single-ended input is to be

used, the VBB output should be connected to the CLK

input and bypassed to ground via a 0.01µF capacitor.

The VBB output is designed to act as the switching

reference for the input of the EL34/L under single-ended

input conditions. As a result, this pin can only source/

sink up to 0.5mA of current.

The common enable (EN) is synchronous so that the

internal dividers will only be enabled/disabled when the

internal clock is already in the LOW state. This avoids

any chance of generating a runt clock pulse on the

internal clock when the device is enabled/disabled as

can happen with an asynchronous control. An internal

runt pulse could lead to losing synchronization between

the internal divider stages. The internal enable flip-flop is

clocked on the falling edge of the divider stages. The

internal enable flip-flop is clocked on the falling edge of

the input clock, therefore, all associated specification

limits are referenced to the negative edge of the clock

input.

PIN NAMES

CLK

VBB

Function

Differential Clock Inputs

Synchronous Enable

Master Reset

Reference Output

Differential ÷2 Outputs

Differential ÷4 Outputs

Differential ÷8 Outputs

Upon start-up, the internal flip-flops will attain a random

state; the master reset (MR) input allows for the

synchronization of the internal dividers, as well as for

multiple EL34/Ls in a system.

Precision Edge is a registered trademark of Micrel, Inc.

Rev.: H

Amendment:/0

M9999-031006

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4 5

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