List of figures
STM8S103K3 STM8S103F3 STM8S103F2
List of figures
Figure 1. Block diagram .........................................................................................................................10
Figure 2. Flash memory organization ....................................................................................................13
Figure 3. STM8S103Kx UFQFPN32/LQFP32 pinout .............................................................................20
Figure 4. STM8S103Kx SDIP32 pinout .................................................................................................21
Figure 5. STM8S103Fx TSSOP20/SO20 pinout ....................................................................................24
Figure 6. STM8S103Fx UFQFPN20-pin pinout .....................................................................................25
Figure 7. Memory map ...........................................................................................................................28
Figure 8. Pin loading conditions .............................................................................................................50
Figure 9. Pin input voltage .....................................................................................................................51
Figure 10. fCPUmax versus VDD ..............................................................................................................54
Figure 11. External capacitor CEXT .......................................................................................................55
Figure 12. Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz .............................................63
Figure 13. Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V ....................................................63
Figure 14. Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz .................................................................64
Figure 15. Typ IDD(WFI) vs. VDD HSE user external clock, fCPU = 16 MHz ..............................................64
Figure 16. Typ IDD(WFI) vs. fCPU HSE user external clock, VDD = 5 V .....................................................65
Figure 17. Typ IDD(WFI) vs. VDD HSI RC osc, fCPU = 16 MHz .................................................................65
Figure 18. HSE external clocksource .....................................................................................................66
Figure 19. HSE oscillator circuit diagram ...............................................................................................67
Figure 20. Typical HSI frequency variation vs VDD @ 4 temperatures ..................................................69
Figure 21. Typical LSI frequency variation vs VDD @ 4 temperatures ...................................................69
Figure 22. Typical VIL and VIH vs VDD @ 4 temperatures ......................................................................72
Figure 23. Typical pull-up resistance vs VDD @ 4 temperatures ............................................................73
Figure 24. Typical pull-up current vs VDD @ 4 temperatures .................................................................73
Figure 25. Typ. VOL @ VDD = 5 V (standard ports) ................................................................................75
Figure 26. Typ. VOL @ VDD = 3.3 V (standard ports) .............................................................................75
Figure 27. Typ. VOL @ VDD = 5 V (true open drain ports) ......................................................................76
Figure 28. Typ. VOL @ VDD = 3.3 V (true open drain ports) ...................................................................76
Figure 29. Typ. VOL @ VDD = 5 V (high sink ports) ................................................................................77
Figure 30. Typ. VOL @ VDD = 3.3 V (high sink ports) .............................................................................77
Figure 31. Typ. VDD - VOH@ VDD = 5 V (standard ports) .......................................................................78
Figure 32. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) ...................................................................78
Figure 33. Typ. VDD - VOH@ VDD = 5 V (high sink ports) .......................................................................79
Figure 34. Typ. VDD - VOH@ VDD = 3.3 V (high sink ports) ....................................................................79
Figure 35. Typical NRST VIL and VIH vs VDD @ 4 temperatures ...........................................................80
Figure 36. Typical NRST pull-up resistance vs VDD @ 4 temperatures .................................................81
Figure 37. Typical NRST pull-up current vs VDD @ 4 temperatures ......................................................81
Figure 38. Recommended reset pin protection ......................................................................................82
Figure 39. SPI timing diagram - slave mode and CPHA = 0 ..................................................................84
Figure 40. SPI timing diagram - slave mode and CPHA = 1 ..................................................................84
Figure 41. SPI timing diagram - master mode(1) ...................................................................................85
Figure 42. Typical application with I2C bus and timing diagram ............................................................89
Figure 43. ADC accuracy characteristics ...............................................................................................89
Figure 44. Typical application with ADC ................................................................................................90
Figure 45. 32-pin low profile quad flat package (7 x 7) ..........................................................................94
Figure 46. 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) ............................................96
Figure 47. 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3) ................................97
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