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STM8S103F2U6TR PDF预览

STM8S103F2U6TR

更新时间: 2024-01-06 09:34:16
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 时钟微控制器外围集成电路
页数 文件大小 规格书
113页 1267K
描述
Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash

STM8S103F2U6TR 技术参数

生命周期:Active零件包装代码:QFN
包装说明:VQCCN, LCC20,.13SQ,20针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.31.00.01Factory Lead Time:14 weeks
风险等级:1.51具有ADC:YES
地址总线宽度:位大小:8
最大时钟频率:16 MHzDAC 通道:NO
DMA 通道:NO外部数据总线宽度:
JESD-30 代码:S-XQCC-N20JESD-609代码:e3
长度:3 mm湿度敏感等级:1
I/O 线路数量:16端子数量:20
片上程序ROM宽度:8最高工作温度:85 °C
最低工作温度:-40 °CPWM 通道:YES
封装主体材料:UNSPECIFIED封装代码:VQCCN
封装等效代码:LCC20,.13SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:3.3/5 V认证状态:Not Qualified
RAM(字节):1024ROM(单词):4096
ROM可编程性:FLASH座面最大高度:0.85 mm
速度:16 MHz子类别:Microcontrollers
最大供电电压:5.5 V最小供电电压:2.95 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLERBase Number Matches:1

STM8S103F2U6TR 数据手册

 浏览型号STM8S103F2U6TR的Datasheet PDF文件第2页浏览型号STM8S103F2U6TR的Datasheet PDF文件第3页浏览型号STM8S103F2U6TR的Datasheet PDF文件第4页浏览型号STM8S103F2U6TR的Datasheet PDF文件第5页浏览型号STM8S103F2U6TR的Datasheet PDF文件第6页浏览型号STM8S103F2U6TR的Datasheet PDF文件第7页 
STM8S103K3 STM8S103F3 STM8S103F2  
Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, data  
EEPROM,10-bit ADC, 3 timers, UART, SPI, I²C  
Permanently active, low consumption power-on  
and power-down reset  
Interrupt management  
Nested interrupt controller with 32 interrupts  
UFQFPN32 5x5  
LQFP32 7x7  
Up to 27 external interrupts on 6 vectors  
Timers  
Advanced control timer: 16-bit, 4 CAPCOM  
channels, 3 complementary outputs, dead-time  
insertion and flexible synchronization  
16-bit general purpose timer, with 3 CAPCOM  
TSSOP20  
SO20W 300 mils  
channels (IC, OC or PWM)  
8-bit basic timer with 8-bit prescaler  
Auto wake-up timer  
UFQFPN20 3x3  
Features  
Core  
Window watchdog and independent watchdog  
timers  
16 MHz advanced STM8 core with Harvard  
architecture and 3-stage pipeline  
Communications interfaces  
UART with clock output for synchronous  
operation, Smartcard, IrDA, LIN master mode  
Extended instruction set  
SPI interface up to 8 Mbit/s  
I2C interface up to 400 Kbit/s  
Memories  
Program memory: 8 Kbytes Flash; data retention  
20 years at 55 °C after 10 kcycles  
Analog to digital converter (ADC)  
Data memory: 640 bytes true data EEPROM;  
endurance 300 kcycles  
10-bit, ±1 LSB ADC with up to 5 multiplexed  
channels, scan mode and analog watchdog  
RAM: 1 Kbytes  
I/Os  
Clock, reset and supply management  
Up to 28 I/Os on a 32-pin package including 21  
high sink outputs  
2.95 to 5.5 V operating voltage  
Flexible clock control, 4 master clock sources:  
Highly robust I/O design, immune against current  
injection  
Low power crystal resonator oscillator  
-
External clock input  
Development support  
-
Embedded single wire interface module  
(SWIM) for fast on-chip programming and  
non intrusive debugging  
Internal, user-trimmable 16 MHz RC  
-
-
Internal low power 128 kHz RC  
-
Clock security system with clock monitor  
Unique ID  
Power management:  
96-bit unique key for each device  
Low power modes (wait, active-halt, halt)  
-
Switch-off peripheral clocks individually  
-
September 2010  
1/113  
DocID15441 Rev 6  
www.st.com  

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