STM32MP157DAA1 PDF预览

STM32MP157DAA1

更新时间: 2025-07-23 17:33:27
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意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
259页 3556K
描述
MPU with Arm Dual Cortex-A7 800 MHz, Arm Cortex-M4 real-time coprocessor, 3D GPU, TFT/MIPI DSI displays, FD-CAN

STM32MP157DAA1 数据手册

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STM32MP157A/D  
Arm® dual Cortex®-A7 800 MHz + Cortex®-M4 MPU, 3D GPU,  
TFT/DSI, 37 comm. interfaces, 29 timers, adv. analog  
Datasheet - production data  
Features  
TFBGA  
LFBGA  
Core  
LFBGA448 (18 × 18mm)  
LFBGA354 (16 × 16mm)  
Pitch 0.8mm  
TFBGA361 (12 × 12 mm)  
TFBGA257 (10 × 10 mm)  
min Pitch 0.5mm  
®
®
32-bit dual-core Arm Cortex -A7  
– L1 32-Kbyte I / 32-Kbyte D for each core  
– 256-Kbyte unified level 2 cache  
Controls for PMIC companion chip  
®
®
®
– Arm NEON™ and Arm TrustZone  
Low-power consumption  
®
®
32-bit Arm Cortex -M4 with FPU/MPU  
®
Total current consumption down to 2 µA  
(Standby mode, no RTC, no LSE, no  
BKPSRAM, no RETRAM)  
– Up to 209 MHz (Up to 703 CoreMark )  
Memories  
External DDR memory up to 1 Gbyte  
– up to LPDDR2/LPDDR3-1066 16/32-bit  
– up to DDR3/DDR3L-1066 16/32-bit  
Clock management  
Internal oscillators: 64 MHz HSI oscillator,  
4 MHz CSI oscillator, 32 kHz LSI oscillator  
708 Kbytes of internal SRAM: 256 Kbytes of  
AXI SYSRAM + 384 Kbytes of AHB SRAM +  
64 Kbytes of AHB SRAM in Backup domain  
and 4 Kbytes of SRAM in Backup domain  
External oscillators: 8-48 MHz HSE oscillator,  
32.768 kHz LSE oscillator  
6 × PLLs with fractional mode  
Dual mode Quad-SPI memory interface  
General-purpose input/outputs  
Flexible external memory controller with up to  
16-bit data bus: parallel interface to connect  
external ICs and SLC NAND memories with up  
to 8-bit ECC  
Up to 176 I/O ports with interrupt capability  
– Up to 8 secure I/Os  
– Up to 6 Wakeup, 3 tampers, 1 active  
tamper  
Security/safety  
Interconnect matrix  
®
TrustZone peripherals, active tamper  
2 bus matrices  
®
Cortex -M4 resources isolation  
®
®
– 64-bit Arm AMBA AXI interconnect, up to  
266 MHz  
Reset and power management  
1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os)  
POR, PDR, PVD and BOR  
®
®
– 32-bit Arm AMBA AHB interconnect, up  
to 209 MHz  
3 DMA controllers to unload the CPU  
On-chip LDOs (RETRAM, BKPSRAM, DSI  
1.2 V, USB 1.8 V, 1.1 V)  
48 physical channels in total  
Backup regulator (~0.9 V)  
1 × high-speed general-purpose master direct  
memory access controller (MDMA)  
Internal temperature sensors  
Low-power modes: Sleep, Stop and Standby  
DDR memory retention in Standby mode  
December 2020  
DS12504 Rev 5  
1/259  
This is information on a product in full production.  
www.st.com  

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