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STK14C88-C45I PDF预览

STK14C88-C45I

更新时间: 2024-01-08 12:02:00
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器军事
页数 文件大小 规格书
20页 713K
描述
32 K x 8 AutoStore nvSRAM Commercial, industrial, military temperatures

STK14C88-C45I 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP32,.3Reach Compliance Code:unknown
ECCN代码:3A001.A.2.CHTS代码:8542.32.00.41
风险等级:5.75Is Samacsys:N
最长访问时间:45 nsJESD-30 代码:R-CDIP-T32
JESD-609代码:e0长度:40.635 mm
内存密度:262144 bit内存集成电路类型:NON-VOLATILE SRAM
内存宽度:8功能数量:1
端子数量:32字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:32KX8封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装等效代码:DIP32,.3
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:4.12 mm最大待机电流:0.0015 A
子类别:SRAMs最大压摆率:0.07 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn85Pb15)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

STK14C88-C45I 数据手册

 浏览型号STK14C88-C45I的Datasheet PDF文件第1页浏览型号STK14C88-C45I的Datasheet PDF文件第2页浏览型号STK14C88-C45I的Datasheet PDF文件第4页浏览型号STK14C88-C45I的Datasheet PDF文件第5页浏览型号STK14C88-C45I的Datasheet PDF文件第6页浏览型号STK14C88-C45I的Datasheet PDF文件第7页 
STK14C88  
Pin Configurations  
Figure 1. Pin Diagram - 32-Pin 300 Mil SOIC/CDIP  
Figure 2. Pin Diagram - 32-Pin 450 Mil LCC  
VCAP  
1
VCC  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A14  
2
HSB  
3
A12  
A7  
W
A13  
A8  
A6  
A5  
A4  
A3  
A13  
A8  
A9  
4
A6  
A5  
A4  
A3  
5
A9  
6
A11  
G
A11  
7
NC  
A2  
(TOP)  
8
G
NC  
A10  
(TOP)  
NC  
A2  
NC  
9
A1  
10  
11  
12  
13  
14  
15  
16  
A10  
A0  
E
A1  
A0  
E
DQ0  
DQ7  
DQ7  
DQ0  
DQ1  
DQ2  
VSS  
DQ6  
DQ5  
DQ4  
DQ3  
Pin Descriptions  
Pin Name  
A14-A0  
DQ7-DQ0  
E
I/O  
Input  
I/O  
Description  
Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array.  
Data: Bi-directional 8-bit data bus for accessing the nvSRAM.  
Chip EnablThe active low E input selects the device.  
Input  
Input  
W
Write Enable: The active low W enables data on the DQ pins to be written to the address  
locatn latched by the falling edge of E.  
G
Input  
utput Enable: The active low G input enables the data output buffers during read cycles.  
De-asserting G high caused the DQ pins to tristate.  
VCC  
Power Suy Power: 5.0V, +10%.  
I/O Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low  
HSB  
external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps  
this pin high if not connected. (optional connection).  
VCAP  
Power Supply AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM  
to nonvolatile storage elements.  
VSS  
NC  
Power Supply Ground.  
No Connect Unlabeled pins have no internal connections.  
Document Number: 001-52038 Rev. *C  
Page 3 of 20  
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