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STK10C48-PF35 PDF预览

STK10C48-PF35

更新时间: 2024-01-08 09:16:48
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管
页数 文件大小 规格书
12页 396K
描述
Non-Volatile SRAM, 2KX8, 35ns, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28

STK10C48-PF35 数据手册

 浏览型号STK10C48-PF35的Datasheet PDF文件第1页浏览型号STK10C48-PF35的Datasheet PDF文件第2页浏览型号STK10C48-PF35的Datasheet PDF文件第4页浏览型号STK10C48-PF35的Datasheet PDF文件第5页浏览型号STK10C48-PF35的Datasheet PDF文件第6页浏览型号STK10C48-PF35的Datasheet PDF文件第7页 
STK10C48  
SRAM READ CYCLES #1 & #2  
(V = 5.0V 10%)  
CC  
SYMBOLS  
NO.  
STK10C48-25 STK10C48-35 STK10C48-45  
PARAMETER  
UNITS  
#1, #2  
Alt.  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time  
25  
35  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ELQV  
ACS  
f
Read Cycle Time  
25  
35  
45  
AVAV  
RC  
AA  
g
3
Address Access Time  
25  
10  
35  
15  
45  
20  
AVQV  
4
Output Enable to Data Valid  
Output Hold after Address Change  
Chip Enable to Output Active  
Chip Disable to Output Inactive  
Output Enable to Output Active  
Output Disable to Output Inactive  
Chip Enable to Power Active  
Chip Disable to Power Standby  
GLQV  
OE  
OH  
LZ  
g
5
5
5
5
5
5
5
AXQX  
6
ELQX  
h
7
10  
10  
25  
13  
13  
35  
15  
15  
45  
EHQZ  
HZ  
8
0
0
0
0
0
0
GLQX  
OLZ  
OHZ  
PA  
h
9
GHQZ  
e
10  
11  
ELICCH  
EHICCL  
d, e  
PS  
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. NE must be high during entire cycle.  
Note g: I/O state assumes E, G < VIL, W > VIH , and NE VIH; device is continuously selected.  
Note h: Measured + 200mV from steady state output voltage.  
f, g  
SRAM READ CYCLE #1: Address Controlled  
2
t
AVAV  
ADDRESS  
3
t
AVQV  
5
t
AXQX  
DQ (DATA OUT)  
DATA VALID  
f
SRAM READ CYCLE #2: E Controlled  
2
t
AVAV  
ADDRESS  
E
1
11  
EHICCL  
t
ELQV  
t
6
t
ELQX  
7
t
EHQZ  
G
9
t
4
GHQZ  
t
GLQV  
8
t
GLQX  
DQ (DATA OUT)  
DATA VALID  
10  
ELICCH  
t
ACTIVE  
STANDBY  
I
CC  
March 2006  
3
Document Control # ML0002 rev 0.2  

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