Datasheet > STC90C514RD+

STC90C514RD+

更新时间： 2024-03-03 10:08:06

品牌	Logo	应用领域
宏晶 - STC		/
页数	文件大小	规格书
269页	1075K
描述
STC90C51RC series MCU

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数据手册

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STC90C514RD+ 数据手册

1.2 Block diagram

The CPU kernel of STC90C51RC/RD+ is fully compatible to the standard 8051 microcontroller, maintains all

instruction mnemonics and binary compatibility. STC90C51RC/RD+ series can execute the fastest instructions

per 6 clock cycles or 12 clock cycles(as the same as the standard 80C51). Improvement of individual programs

depends on the actual instructions used.

RAM ADDR

AUX-RAM

1024 Byte

256 Byte

RAM

FLASH

64K

Stack

Poniter

Dual Data

Poniter

B Register

ACC

TMP2

TMP1

Timer 0/1

Timer 2

UART

ISP/IAP

Address

Generator

ALU

EEPROM

Program

Counter

WDT

PSW

PSEN

ALE

Port 0,1,2,3,4

Latch

Control

Unit

RESET

Port 0,1,2,3,4

Driver

XTAL1

XTAL2

P0, P1,P2,P3,P4

STC90C51RC/RD+ Block Diagram

ꢆ

STC MCU Limited.

1...4 5 678 9 10...269

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