Datasheet > STC62WV5128D

STC62WV5128D

更新时间： 2024-03-03 10:09:12

品牌	Logo	应用领域
宏晶 - STC		/
页数	文件大小	规格书
10页	373K
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数据手册

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STC62WV5128D 数据手册

STC

STC62WV5128

KEY TO SWITCHING WAVEFORMS

AC TEST CONDITIONS

(Test Load and Input/Output Reference)

Input Pulse Levels

Vcc / 0V

WAVEFORM

INPUTS

OUTPUTS

MUST BE

STEADY

MUST BE

STEADY

Input Rise and Fall Times

1V/ns

MAY CHANGE

FROM H TO L

WILL BE

CHANGE

FROM H TO L

Input and Output

Timing Reference Level

0.5Vcc

MAY CHANGE

FROM L TO H

WILL BE

CHANGE

FROM L TO H

Output Load

C_L= 30pF+1TTL

C_L= 100pF+1TTL

DON T CARE:

CHANGE :

STATE

UNKNOWN

ANY CHANGE

PERMITTED

DOES NOT

APPLY

CENTER

LINE IS HIGH

IMPEDANCE

”OFF ”STATE

AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85^oC )

READ CYCLE

JEDEC

PARAMETER

NAME

CYCLE TIME : 70ns

(Vcc = 2.7~5.5V)

MIN. TYP. MAX.

CYCLE TIME : 55ns

(Vcc = 3.0~5.5V)

PARAMETER

DESCRIPTION

Read Cycle Time

UNIT

NAME

MIN.

TYP.

MAX.

t_AVAX

t_AVQV

t_ELQV

t_GLQV

t_ELQX

t_GLQX

t_EHQZ

t_GHQZ

t_RC

t_AA

Address Access Time

t_ACS

t_OE

Chip Select Access Time

Output Enable to Output Valid

Chip Select to Output Low Z

Output Enable to Output in Low Z

Chip Deselect to Output in High Z

Output Disable to Output in High Z

t_CLZ

t_OLZ

t_CHZ

t_OHZ

t_AXOX

t_OH

Data Hold from Address Change

SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1 ^(1,2,4)

ADDRESS

D _OUT

Revision 1.1

Jan. 2004

R0201-STC62WV5128

1 2 345 6 7...10

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