SSM2602
Table 5. Digital Audio Interface Slave Mode Timing
Limit
Parameter
tMIN
10
10
10
10
tMAX
Unit
ns
ns
ns
ns
Description
tDS
tDH
tLRSU
tLRH
tDD
PBDAT setup time from BCLK rising edge
PBDAT hold time from BCLK rising edge
RECLRC/PBLRC setup time to BCLK rising edge
RECLRC/PBLRC hold time to BCLK rising edge
RECDAT propagation delay from BCLK falling edge (external
load of 70 pF)
30
ns
tBCH
tBCL
tBCY
25
25
50
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
BCLK cycle time
tBCH tBCL
tBCY
BCLK
PBLRC/
RECLRC
tDS tLRH tLRSU
PBDAT
tDH
tDD
RECDAT
Figure 4. Digital Audio Interface Slave Mode Timing
Table 6. Digital Audio Interface Master Mode Timing
Limit
Parameter
tDST
tDHT
tDL
tDDA
tBCLKR
tBCLKF
tBCLKDS
tMIN
30
10
tMAX
Unit
ns
ns
ns
ns
Description
PBDAT setup time to BCLK rising edge
PBDAT hold time to BCLK rising edge
RECLRC/PBLRC propagation delay from BCLK falling edge
RECDAT propagation delay from BCLK falling edge
BCLK rising time (10 pF load)
10
10
10
10
45:55:00
ns
ns
BCLK falling time (10 pF load)
BCLK duty cycle (normal and USB mode)
55:45:00
BCLK
tDL
PBLRC/
RECLRC
tDST tDHT
PBDAT
tDDA
RECDAT
Figure 5. Digital Audio Interface Master Mode Timing
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