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SPT9689ACU PDF预览

SPT9689ACU

更新时间: 2024-01-04 08:44:10
品牌 Logo 应用领域
CADEKA 比较器
页数 文件大小 规格书
8页 164K
描述
DUAL ULTRAFAST VOLTAGE COMPARATOR

SPT9689ACU 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:SIDE BRAZED, DIP-16Reach Compliance Code:unknown
风险等级:5.79放大器类型:COMPARATOR
最大平均偏置电流 (IIB):38 µA25C 时的最大偏置电流 (IIB):25 µA
最大输入失调电压:30000 µVJESD-30 代码:R-CDIP-T16
JESD-609代码:e0负供电电压上限:-6 V
标称负供电电压 (Vsup):-5.2 V功能数量:2
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出类型:OPEN-EMITTER
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:5,-5.2 V
认证状态:Not Qualified标称响应时间:0.75 ns
子类别:Comparator供电电压上限:6 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:BIPOLAR温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
Base Number Matches:1

SPT9689ACU 数据手册

 浏览型号SPT9689ACU的Datasheet PDF文件第2页浏览型号SPT9689ACU的Datasheet PDF文件第3页浏览型号SPT9689ACU的Datasheet PDF文件第4页浏览型号SPT9689ACU的Datasheet PDF文件第5页浏览型号SPT9689ACU的Datasheet PDF文件第7页浏览型号SPT9689ACU的Datasheet PDF文件第8页 
TYPICAL INTERFACE CIRCUIT  
to decrease parasitic feedback. If the output board traces  
are longer than approximately half an inch, microstripline  
techniques must be employed to prevent ringing on the  
output waveform. Also, the microstriplines must be termi-  
nated at the far end with the characteristic impedance of  
the line to prevent reflections. Both supply voltage pins  
should be decoupled with high-frequency capacitors as  
close to the device as possible. All ground pins and no  
connects should be soldered to a common ground plane  
The typical interface circuit using the comparator is shown  
in figure 3. Although it needs few external components  
and is easy to apply, there are several conditions that  
should be noted to achieve optimal performance.The very  
high operating speeds of the comparator require careful  
layout, decoupling of supplies, and proper design of trans-  
mission lines.  
Since the SPT9689 comparator is a very high-frequency to further improve noise immunity. If using the SPT9689  
and high-gain device, certain layout rules must be fol- as a single comparator, the outputs of the inactive com-  
lowed to avoid oscillations. The comparator should be parator can be grounded, left open, or terminated with  
soldered to the board with component lead lengths kept 50 ohms to 2 V. All outputs on the active comparator,  
as short as possible. A ground plane should be used while whether used or unused, should have identical termina-  
the input impedance to the part is kept as low as possible tions to minimize ground current switching transients.  
Figure 4 – SPT9689 Typical Interface Circuit  
with Hysteresis  
Figure 3 – SPT9689 Typical Interface Circuit  
+5.0 V  
–2 V  
+5.0 V  
0 to 200 W  
100 W  
–1.3 V  
ECL  
10 µF  
0.1 µF  
100 pF  
10 µF  
0.1 µF  
100 pF  
+V  
+V  
CC  
CC  
V
V
IN  
+
IN  
+
LE  
LE  
LE  
LE  
Q Output  
Q Output  
Q Output  
Q Output  
GND  
GND  
V
EE  
V
REF  
V
V
EE  
REF  
R
R
L
L
50 W  
50  
W
100 pF  
0.1 µF  
100 pF  
0.1 µF  
10 µF  
R
L
R
L
50 W  
100 pF  
100 pF  
10 µF  
0.1 µF  
50  
W
0.1 µF  
10 µF  
10 µF  
10  
F
10 µF  
–5.2 V  
–2 V  
–5.2 V  
–2 V  
NOTES:  
NOTES:  
Denotes ground plane.  
Ferrite bead. Fair Rite Part # 2643001501.  
All resistors are chip type 1%.  
Denotes ground plane.  
Ferrite bead. Fair Rite Part # 2643001501.  
All resistors are chip type 1%.  
0.1 µF and 100 pF capacitors are chip type mounted as close  
to the pins as possible.  
0.1 µF and 100 pF capacitors are chip type mounted  
as close to the pins as possible.  
10 µF tant capacitors have lead lengths <0.25" long.  
Represents line termination.  
10 µF tant capacitors have lead lengths <0.25" long.  
Represents line termination.  
SPT9689  
6
2/20/01  

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