Datasheet > SPC5602DF1CLH3

SPC5602DF1CLH3

更新时间： 2024-01-18 18:36:34

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
83页	1557K
描述
NXP 32-bit MCU, Power Arch core, 256KB Flash, 32MHz, -40/+85degC, Automotive Grade, QFP 64

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SPC5602DF1CLH3 数据手册

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MPC5602D

Rev. 6, 01/2013

MPC5602D

100 LQFP

14 mm x 14 mm

64 LQFP

10 mm x 10 mm

MPC5602D Microcontroller

Data Sheet

•

Up to 79 configurable general purpose pins

supporting input and output operations (package

dependent)

•

Single issue, 32-bit CPU core complex (e200z0h)

— Compliant with the Power Architecture

embedded category

Real Time Counter (RTC) with clock source from

128 kHz or 16 MHz internal RC oscillator

supporting autonomous wakeup with 1 ms

resolution with max timeout of 2 seconds

— Includes an instruction set enhancement

allowing variable length encoding (VLE) for

code size footprint reduction. With the optional

encoding of mixed 16-bit and 32-bit

•

Up to 4 periodic interrupt timers (PIT) with 32-bit

counter resolution

instructions, it is possible to achieve significant

code size footprint reduction.

•

1 System Timer Module (STM)

•

Up to 256 KB on-chip Code Flash supported with

Flash controller and ECC

Nexus development interface (NDI) per IEEE-ISTO

5001-2003 Class 1 standard

•

64 KB on-chip Data Flash with ECC

Up to 16 KB on-chip SRAM with ECC

•

Device/board boundary Scan testing supported with

per Joint Test Action Group (JTAG) of IEEE (IEEE

1149.1)

Interrupt controller (INTC) with multiple interrupt

vectors, including 20 external interrupt sources and

18 external interrupt/wakeup sources

On-chip voltage regulator (VREG) for regulation of

input supply for all internal levels

•

Frequency modulated phase-locked loop (FMPLL)

Crossbar switch architecture for concurrent access to

peripherals, Flash, or SRAM from multiple bus

masters

•

Boot assist module (BAM) supports internal Flash

programming via a serial link (CAN or SCI)

Timer supports input/output channels providing a

range of 16-bit input capture, output compare, and

pulse width modulation functions (eMIOS-lite)

•

Up to 33 channel 12-bit analog-to-digital converter

(ADC)

•

2 serial peripheral interface (DSPI) modules

3 serial communication interface (LINFlex) modules

— LINFlex 1 and 2: Master capable

— LINFlex 0: Master capable and slave capable;

connected to eDMA

•

1 enhanced full CAN (FlexCAN) module with

configurable buffers

This document contains information on a new product. Specifications and information herein

are subject to change without notice.

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