THEORY OF OPERATION
safely begin down conversion, and an inter-
nal VCC UVLO ensures that the controller
itselfhasenoughvoltagetoproperlyoperate.
Other protection features include thermal
shutdown and short-circuit detection. In the
event that either a thermal, short-circuit, or
UVLOfaultisdetected,theSP765ꢀisforced
intoanidlestatewheretheoutputdriversare
held off for a finite period before a re-start
is attempted.
Thermal and Short-Circuit
Protection
Because the SP765ꢀ is designed to drive
largeoutputcurrent,thereisachancethatthe
power converter will become too hot. There-
fore, an internal thermal shutdown (145°C)
has been included to prevent the IC from
malfunctioning at extreme temperatures.
A short-circuit detection comparator has
also been included in the SP765ꢀ to protect
against an accidental short at the output
of the power converter. This comparator
constantly monitors the positive and nega-
tive terminals of the error amplifier, and if
the VFB pin falls more than 250mV (typical)
below the positive reference, a short-circuit
faultisset.BecausetheSSpinoverridesthe
internal 0.8V reference during soft start, the
SP765ꢀ is capable of detecting short-circuit
faults throughout the duration of soft start as
well as in regular operation.
Soft Start
“Soft Start” is achieved when a power con-
verter ramps up the output voltage while
controlling the magnitude of the input sup-
ply source current. In a modern step down
converter, ramping up the positive terminal
of the error amplifier controls soft start. As a
result,excesssourcecurrentcanbedefined
as the current required to charge the output
capacitor.
IVIN = COUT * (∆VOUT / ∆TSOFT-START
)
Handling of Faults:
The SP765ꢀ provides the user with the op-
tion to program the soft start rate by tying
a capacitor from the SS pin to GND. The
selection of this capacitor is based on the
ꢀ0µA pullup current present at the SS pin
and the 0.8V reference voltage. Therefore,
the excess source can be redefined as:
Upon the detection of power (UVLO), ther-
mal, or short-circuit faults, the SP765ꢀ is
forced into an idle state where the SS and
COMP pins are pulled low and the NFETS
are held off. In the event of UVLO fault, the
SP765ꢀ remains in this idle state until the
UVLO fault is removed. Upon the detection
of a thermal or short-circuit fault, an internal
200ms timer is activated. In the event of a
short-circuit fault, a re-start is attempted im-
mediately after the 200ms timeout expires.
Whereas, when a thermal fault is detected
the200msdelaycontinuouslyrecyclesanda
re-startcannotbeattempteduntilthethermal
fault is removed and the timer expires.
IVIN = COUT * (∆VOUT *ꢀ0µA / (CSS * 0.8V)
Under Voltage Lock Out (UVLO)
The SP765ꢀ contains two separate UVLO
comparatorstomonitortheinternalbias(VCC
)
andconversion(VIN)voltagesindependently.
The VCC UVLO threshold is internally set
to 4.25V, whereas the VIN UVLO threshold
is programmable through the UVIN pin.
When the UVIN pin is greater than 2.5V,
the SP765ꢀ is permitted to start up pend-
ing the removal of all other faults. Both the
VCC and VIN UVLO comparators have been
designed with hysteresis to prevent noise
from resetting a fault.
Error Amplifier and Voltage Loop
Since the heart of the SP765ꢀ voltage error
loop is a high performance, wide bandwidth
transconductance amplifier, great care
shouldbetakentoselecttheoptimalcompen-
sation network. Because of the amplifier’s
Rev J: 3/ꢀ4/07
SP765ꢀ Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2007 Sipex Corporation
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