PIN DESCRIPTION
Pin #
ꢀ-3
Pin Name Description
Pgnd
Ground connection for the synchronous rectifier
4,8,ꢀ9-2ꢀ
GND
Ground Pin. The control circuitry of the IC and lower power driver are refer-
enced to this pin. Return separately from other ground traces to the (-) terminal
of Cout.
5
6
Vfb
Feedback Voltage and Short Circuit Detection pin. It is the inverting input of the
Error Amplifier and serves as the output voltage feedback point for the Buck
Converter. The output voltage is sensed and can be adjusted through an exter-
nal resistor divider. Whenever Vfb drops 0.25V below the positive reference, a
short circuit fault is detected and the IC enters hiccup mode.
COMP
Output of the Error Amplifier. It is internally connected to the inverting input of
the PWM comparator. An optimal filter combination is chosen and connected
to this pin and either ground or Vfb to stabilize the voltage mode loop.
7
9
UVIN
SS
UVLO input for Vin voltage. Connect a resistor divider between Vin and UVin to
set minimum operating voltage.
Soft Start. Connect an external capacitor between SS and GND to set the soft
start rate based on the ꢀ0µA source current. The SS pin is held low via a ꢀmA
(min) current during all fault conditions.
ꢀ0-ꢀ3
Vin
Input connection to the high side N-channel MOSFET. Place a decoupling
capacitor between this pin and Pgnd.
ꢀ4-ꢀ6,23-26
LX
NC
Connect an inductor between this pinand Vout
ꢀ7
ꢀ8
No Connect
BST
High side driver supply pin. Connect BST to the external boost diode and ca-
pacitor as shown in the Typical Application Circuit on page ꢀ. High side driver
is connected between BST pin and SWN pin.
22
Vcc
Input for external 5V bias supply
THEORY OF OPERATION
General Overview
that accurately sets the PWM frequency to
900kHz.
The SP7651 is a fixed frequency, voltage
mode, synchronous PWM regulator opti-
mized for high efficiency. The part has been
designed to be especially attractive for split
plane applications utilizing 5V to power the
controller and 2.5V to 20V for step down
conversion.
The SP765ꢀ contains two unique control
features that are very powerful in distributed
applications.First,asynchronousdrivercon-
trol is enabled during startup, to prohibit the
low side NFET from pulling down the output
until the high side NFET has attempted to
turn on. Second, a 100% duty cycle timeout
ensuresthatthelowsideNFETisperiodically
enhanced during extended periods at 100%
dutycycle.Thisguaranteesthesynchronized
refreshing of the BST capacitor during very
large duty ratios.
TheheartoftheSP765ꢀisawidebandwidth
transconductance amplifier designed to ac-
commodate Type II and Type III compensa-
tion schemes. A precision 0.8V reference,
present on the positive terminal of the error
amplifier, permits the programming of the
output voltage down to 0.8V via the VFB pin.
The output of the error amplifier, COMP,
which is compared to a ꢀ.ꢀV peak-to-peak
ramp, is responsible for trailing edge PWM
control.Thisvoltageramp,andPWMcontrol
logic are governed by the internal oscillator
The SP765ꢀ also contains a number of
valuableprotectionfeatures.Programmable
UVLO allows the user to set the exact VIN
value at which the conversion voltage can
Rev J: 3/ꢀ4/07
SP765ꢀ Wide Input Voltage Range 3A, 900kHz, Buck Regulator
© Copyright 2007 Sipex Corporation
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