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SP6337EK1-L-R-C-A PDF预览

SP6337EK1-L-R-C-A

更新时间: 2023-01-03 10:39:52
品牌 Logo 应用领域
艾科嘉 - EXAR 光电二极管
页数 文件大小 规格书
33页 1432K
描述
Power Supply Management Circuit, Adjustable, 1 Channel, PDSO8, LEAD FREE, MO-193BA, TSOT-8

SP6337EK1-L-R-C-A 数据手册

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PIN DESCRIPTION  
Pin #  
Name  
V1  
Description  
First supply voltage input. Also powers internal circuitry. Trip threshold  
voltage is internally set.  
1
2
V2  
Second supply voltage input. Trip threshold voltage internally set.  
Power Fail Input pin. Trip threshold is 0.5V. When the input voltage at  
the PFI pin is <0.5V, PFOB is low. Connect to GND or V1 if not used.  
3
PFI  
4
5
6
V3  
Input for the third supply voltage. Trip threshold is 0.5V.  
Power Fail Output pin. Active low open drain output. When the input  
voltage at the PFI pin is <0.5V, PFOB is low.  
PFOB  
GND  
Common ground reference pin.  
Watch-Dog Input pin. When no transition is detected at the WDI pin for  
the duration of WDI timeout period, reset is asserted. Leave open if not  
used. RST/RSTB output is used to signal watchdog timeout overflow,  
and its output pulses high/low (depending on the active reset polarity)  
for the reset timeout period after each watchdog timeout overflow. The  
watchdog timer clears whenever the reset is asserted or manual reset  
is asserted or a transition is observed at WDI pin. Watchdog timer  
functionality can be disabled by leaving this input floating.  
7
WDI  
Reset output. Open-Drain or CMOS, active high or low. Reset is  
asserted when any of the three supply inputs is below its trip threshold.  
It stays asserted for 200 ms (typical / default) after the last supply input  
traverses its trip threshold. Reset is guaranteed to be in the correct  
state for V1>0.9V. RST/RSTB asserts when V1 or V2 or V3 drop below  
their corresponding reset thresholds, or the watchdog timer triggers a  
reset. RST/RSTB remains asserted for the reset timeout period after  
V1 and V2 and V3 exceed their corresponding reset thresholds. Open-  
drain outputs require an external pull-up resistor. CMOS outputs are  
referenced to V1.  
8
RST/RSTB  
Jun 4-06 Rev H  
SP6336-SP6337-SP6338 Triple µPower Supervisory Circuit  
© 2007 Sipex Corporation  
5

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