Table of Contents
1.0 General Description ......................................................................................................................... 1
2.0 Target Applications .......................................................................................................................... 1
3.0 Features ........................................................................................................................................ 1
TABLE 1. Device Configuration Information .............................................................................................. 2
TABLE 2. Device Output Format Information ............................................................................................ 2
TABLE 3. Example Configurations for Common Frequencies ...................................................................... 2
4.0 Functional Block Diagram ................................................................................................................. 3
5.0 Connection Diagram ........................................................................................................................ 6
6.0 Pin Descriptions ............................................................................................................................. 7
7.0 Absolute Maximum Ratings .............................................................................................................. 9
8.0 Package Thermal Resistance ............................................................................................................ 9
9.0 Recommended Operating Conditions ................................................................................................ 9
10.0 Electrical Characteristics ............................................................................................................... 10
11.0 Serial Data Timing Diagram .......................................................................................................... 17
12.0 Charge Pump Current Specification Definitions ................................................................................ 17
12.1 CHARGE PUMP OUTPUT CURRENT MAGNITUDE VARIATION VS. CHARGE PUMP OUTPUT
VOLTAGE ................................................................................................................................ 18
12.2 CHARGE PUMP SINK CURRENT VS. CHARGE PUMP OUTPUT SOURCE CURRENT
MISMATCH .............................................................................................................................. 18
12.3 CHARGE PUMP OUTPUT CURRENT MAGNITUDE VARIATION VS. TEMPERATURE ................ 18
13.0 Differential Voltage Measurement Terminology (Note 24) .................................................................. 19
14.0 Typical Performance Characteristics .............................................................................................. 19
14.1 CLOCK OUTPUT AC CHARACTERISTICS ............................................................................. 19
15.0 Features ..................................................................................................................................... 21
15.1 SYSTEM ARCHITECTURE ................................................................................................... 21
15.2 REDUNDANT REFERENCE INPUTS (CLKin0/CLKin0*, CLKin1/CLKin1*) ................................... 21
15.3 PLL1 CLKinX (X=0,1) LOSS OF SIGNAL (LOS) ....................................................................... 21
15.4 INTEGRATED LOOP FILTER POLES ..................................................................................... 21
15.5 CLOCK DISTRIBUTION ....................................................................................................... 21
15.6 CLKout DIVIDE (CLKoutX_DIV, X = 0 to 4) .............................................................................. 21
15.7 GLOBAL CLOCK OUTPUT SYNCHRONIZATION (SYNC*) ....................................................... 21
15.8 GLOBAL OUTPUT ENABLE AND LOCK DETECT .................................................................... 21
16.0 Functional Description .................................................................................................................. 22
16.1 ARCHITECTURAL OVERVIEW .............................................................................................. 22
16.2 PHASE DETECTOR 1 (PD1) ................................................................................................. 22
16.3 PHASE DETECTOR 2 (PD2) ................................................................................................. 22
16.4 PLL2 FREQUENCY DOUBLER .............................................................................................. 22
16.5 INPUTS / OUTPUTS ............................................................................................................. 22
16.5.1 PLL1 Reference Inputs (CLKin0 / CLKin0*, CLKin1 / CLKin1*) .......................................... 22
16.5.2 PLL2 OSCin / OSCin* Port ........................................................................................... 22
16.5.3 CPout1 / CPout2 ........................................................................................................ 22
16.5.4 Fout .......................................................................................................................... 22
16.5.5 Digital Lock Detect 1 Bypass ........................................................................................ 23
16.5.6 Bias .......................................................................................................................... 23
17.0 General Programming Information ................................................................................................. 24
17.1 RECOMMENDED PROGRAMMING SEQUENCE .................................................................... 24
17.2 DEFAULT DEVICE REGISTER SETTINGS AFTER POWER ON/RESET .................................... 27
17.3 REGISTER R0 TO R4 ........................................................................................................... 28
17.3.1 CLKoutX_DIV: Clock Channel Divide Registers .............................................................. 28
17.3.2 EN_CLKoutX: Clock Channel Output Enable .................................................................. 28
17.3.3 CLKoutX/CLKoutX* LVCMOS Mode Control ................................................................... 28
17.3.4 CLKoutX/CLKoutX* LVPECL Mode Control .................................................................... 29
17.3.5 CLKoutX_MUX: Clock Output Mux ................................................................................ 29
17.4 REGISTERS 5, 6 .................................................................................................................. 29
17.5 REGISTER 7 ....................................................................................................................... 29
17.5.1 RESET bit ................................................................................................................. 29
17.6 REGISTERS 8, 9 .................................................................................................................. 29
17.7 REGISTER 10 ..................................................................................................................... 29
17.7.1 RC_DLD1_Start: PLL1 Digital Lock Detect Run Control bit ............................................... 29
17.8 REGISTER 11 ..................................................................................................................... 29
17.8.1 CLKinX_BUFTYPE: PLL1 CLKinX/CLKinX* Buffer Mode Control ...................................... 29
17.8.2 CLKin_SEL: PLL1 Reference Clock Selection and Revertive Mode Control Bits .................. 30
17.8.3 CLKinX_LOS ............................................................................................................. 30
17.8.4 PLL1 Reference Clock LOS Timeout Control .................................................................. 30
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