Datasheet > SN74LVC2G34_08

SN74LVC2G34_08

更新时间： 2024-01-21 21:37:47

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
16页	748K
描述
DUAL BUFFER GATE

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数据手册

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SN74LVC2G34_08 数据手册

SN74LVC2G34

DUAL BUFFER GATE

www.ti.com

SCES359H–AUGUST 2001–REVISED FEBRUARY 2007

FEATURES

•

Available in the Texas Instruments

NanoFree™ Package

•

Typical V_OHV(Output V_OHUndershoot)

>2 V at V_CC= 3.3 V, T_A= 25°C

•

Supports 5-V V_CCOperation

I_offSupports Partial-Power-Down Mode

Operation

Inputs Accept Voltages to 5.5 V

Max t_pdof 4.1 ns at 3.3 V

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

Low Power Consumption, 10-µA Max I_CC

±24-mA Output Drive at 3.3 V

ESD Protection Exceeds JESD 22

–

2000-V Human-Body Model (A114-A)

200-V Machine Model (A115-A)

Typical V_OLP(Output Ground Bounce)

<0.8 V at V_CC= 3.3 V, T_A= 25°C

1000-V Charged-Device Model (C101)

DBV PACKAGE

(TOP VIEW)

DCK PACKAGE

(TOP VIEW)

DRL PACKAGE

(TOP VIEW)

YZP PACKAGE

(BOTTOM VIEW)

GND

See mechanical drawings for dimensions.

DESCRIPTION/ORDERING INFORMATION

This dual buffer gate is designed for 1.65-V to 5.5-V V_CCoperation. The SN74LVC2G34 performs the Boolean

function Y = A in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

This device is fully specified for partial-power-down applications using I_off. The I_offcircuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

ORDERABLE PART NUMBER

TOP-SIDE MARKING⁽²⁾

NanoFree™ – WCSP (DSBGA)

Reel of 3000

SN74LVC2G34YZPR

_ _ _C9_

0.23-mm Large Bump – YZP (Pb-free)

SOT (SOT-23) – DBV

Reel of 3000

Reel of 250

Reel of 3000

Reel of 250

Reel of 4000

SN74LVC2G34DBVR

SN74LVC2G34DBVT

SN74LVC2G34DCKR

SN74LVC2G34DCKT

SN74LVC2G34DRLR

C34_

–40°C to 85°C

SOT (SC-70) – DCK

C9_

SOT (SOT-533) – DRL

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.

YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoFree is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...16

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与SN74LVC2G34_08相关器件

型号	品牌	获取价格	描述	数据表
SN74LVC2G34DBV	TI	获取价格	NON-INVERT GATE
SN74LVC2G34DBVR	TI	获取价格	DUAL BUFFER GATE
SN74LVC2G34DBVR	UMW	获取价格	逻辑集成电路
SN74LVC2G34DBVRE4	TI	获取价格	DUAL BUFFER GATE
SN74LVC2G34DBVRG4	TI	获取价格	DUAL BUFFER GATE
SN74LVC2G34DBVT	TI	获取价格	DUAL BUFFER GATE
SN74LVC2G34DBVTG4	TI	获取价格	DUAL BUFFER GATE
SN74LVC2G34DCK	TI	获取价格	NON-INVERT GATE
SN74LVC2G34DCK3	TI	获取价格	2 通道、1.65V 至 5.5V 缓冲器 \| DCK \| 6 \| -40 to 85
SN74LVC2G34DCKR	TI	获取价格	DUAL BUFFER GATE

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