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SN74LVC2G34DCK3 PDF预览

SN74LVC2G34DCK3

更新时间: 2023-06-19 15:16:36
品牌 Logo 应用领域
德州仪器 - TI 光电二极管逻辑集成电路栅极
页数 文件大小 规格书
16页 748K
描述
2 通道、1.65V 至 5.5V 缓冲器 | DCK | 6 | -40 to 85

SN74LVC2G34DCK3 技术参数

是否Rohs认证: 不符合生命周期:Active
包装说明:TSSOP,Reach Compliance Code:compliant
Factory Lead Time:6 weeks风险等级:1.97
Samacsys Description:Specialty Function Logic Dual Buffer Gate 6-SC70 -40 to 85系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G6JESD-609代码:e6
长度:2 mm逻辑集成电路类型:BUFFER
最大I(ol):0.032 A湿度敏感等级:1
功能数量:2输入次数:1
端子数量:6最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH最大电源电流(ICC):0.01 mA
传播延迟(tpd):8.6 ns座面最大高度:1.1 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Bismuth (Sn/Bi)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:1.25 mm

SN74LVC2G34DCK3 数据手册

 浏览型号SN74LVC2G34DCK3的Datasheet PDF文件第2页浏览型号SN74LVC2G34DCK3的Datasheet PDF文件第3页浏览型号SN74LVC2G34DCK3的Datasheet PDF文件第4页浏览型号SN74LVC2G34DCK3的Datasheet PDF文件第5页浏览型号SN74LVC2G34DCK3的Datasheet PDF文件第6页浏览型号SN74LVC2G34DCK3的Datasheet PDF文件第7页 
SN74LVC2G34  
DUAL BUFFER GATE  
www.ti.com  
SCES359HAUGUST 2001REVISED FEBRUARY 2007  
FEATURES  
Available in the Texas Instruments  
NanoFree™ Package  
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
Supports 5-V VCC Operation  
Ioff Supports Partial-Power-Down Mode  
Operation  
Inputs Accept Voltages to 5.5 V  
Max tpd of 4.1 ns at 3.3 V  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
ESD Protection Exceeds JESD 22  
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
1000-V Charged-Device Model (C101)  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(BOTTOM VIEW)  
3
2
1
4
5
6
2Y  
2A  
GND  
1A  
1
2
3
6
5
4
1A  
GND  
2A  
1Y  
1A  
GND  
2A  
1Y  
1
2
3
6
5
4
1
2
3
6
1A  
1Y  
V
V
CC  
V
CC  
V
CC  
1Y  
2Y  
GND  
5
4
CC  
2Y  
2Y  
2A  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This dual buffer gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2G34 performs the Boolean  
function Y = A in positive logic.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
NanoFree™ – WCSP (DSBGA)  
Reel of 3000  
SN74LVC2G34YZPR  
_ _ _C9_  
0.23-mm Large Bump – YZP (Pb-free)  
SOT (SOT-23) – DBV  
Reel of 3000  
Reel of 250  
Reel of 3000  
Reel of 250  
Reel of 4000  
SN74LVC2G34DBVR  
SN74LVC2G34DBVT  
SN74LVC2G34DCKR  
SN74LVC2G34DCKT  
SN74LVC2G34DRLR  
C34_  
–40°C to 85°C  
SOT (SC-70) – DCK  
C9_  
C9_  
SOT (SOT-533) – DRL  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.  
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2001–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

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