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SN74LVC16374DLR PDF预览

SN74LVC16374DLR

更新时间： 2024-01-05 21:31:44
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德州仪器 - TI 触发器输出元件
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SN74LVC16374DLR 数据手册

 浏览型号SN74LVC16374DLR的Datasheet PDF文件第2页浏览型号SN74LVC16374DLR的Datasheet PDF文件第3页浏览型号SN74LVC16374DLR的Datasheet PDF文件第4页浏览型号SN74LVC16374DLR的Datasheet PDF文件第5页浏览型号SN74LVC16374DLR的Datasheet PDF文件第6页 
SN74LVC16374  
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
SCAS316B – NOVEMBER 1993 – REVISED JULY 1995  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1CLK  
1D1  
1D2  
GND  
1D3  
1D4  
2
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
3
= 3.3 V, T = 25°C  
CC  
A
4
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
5
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
6
A
7
Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
V
V
CC  
CC  
8
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
9
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
description  
This 16-bit edge-triggered D-type flip-flop is  
designed for 2.7-V to 3.6-V V operation.  
V
V
CC  
CC  
CC  
2Q5  
2Q6  
GND  
2Q7  
2Q8  
2OE  
2D5  
2D6  
GND  
2D7  
2D8  
2CLK  
The SN74LVC16374 is particularly suitable for  
implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers. It  
can be used as two 8-bit flip-flops or one 16-bit  
flip-flop. On the positive transition of the clock  
(CLK) input, the Q outputs of the flip-flop take on  
the logic levels set up at the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus  
lines without need for interface or pullup components.  
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74LVC16374 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
123456

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SN74LVC16374DLR 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC16374DGGR TI

完全替代

 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 48-TSSOP -40 to 85
SN74LVC16374DL TI

类似代替

 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC16374ADLR TI

类似代替

 16 BIT EDGE TRIGGERED D TYPE FLIP FLOP WITH 3 STATE OUTPUTS

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