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SN74LS166M PDF预览

SN74LS166M

更新时间: 2024-11-06 20:08:03
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
8页 80K
描述
IC LS SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, EIAJ, SOP-16, Shift Register

SN74LS166M 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.24
计数方向:RIGHT系列:LS
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:10.2 mm逻辑集成电路类型:PARALLEL IN SERIAL OUT
最大频率@ Nom-Sup:25000000 Hz湿度敏感等级:1
位数:8功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):35 ns
认证状态:Not Qualified座面最大高度:2.05 mm
子类别:Shift Registers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:5.275 mm
最小 fmax:25 MHzBase Number Matches:1

SN74LS166M 数据手册

 浏览型号SN74LS166M的Datasheet PDF文件第2页浏览型号SN74LS166M的Datasheet PDF文件第3页浏览型号SN74LS166M的Datasheet PDF文件第4页浏览型号SN74LS166M的Datasheet PDF文件第5页浏览型号SN74LS166M的Datasheet PDF文件第6页浏览型号SN74LS166M的Datasheet PDF文件第7页 
SN74LS166  
8-Bit Shift Registers  
The SN74LS166 is an 8-Bit Shift Register. Designed with all inputs  
buffered, the drive requirements are lowered to one 74LS standard  
load. By utilizing input clamping diodes, switching transients are  
minimized and system design simplified.  
The LS166 is a parallel-in or serial-in, serial-out shift register and  
has a complexity of 77 equivalent gates with gated clock inputs and an  
overriding clear input. The shift/load input establishes the parallel-in  
or serial-in mode. When high, this input enables the serial data input  
and couples the eight flip-flops for serial shifting with each clock  
pulse. Synchronous loading occurs on the next clock pulse when this is  
low and the parallel data inputs are enabled. Serial data flow is  
inhibited during parallel loading. Clocking is done on the low-to-high  
level edge of the clock pulse via a two input positive NOR gate, which  
permits one input to be used as a clock enable or clock inhibit function.  
Clocking is inhibited when either of the clock inputs are held high,  
holding either input low enables the other clock input. This will allow  
the system clock to be free running and the register stopped on  
command with the other clock input. A change from low-to-high on  
the clock inhibit input should only be done when the clock input is  
high. A buffered direct clear input overrides all other inputs, including  
the clock, and sets all flip-flops to zero.  
http://onsemi.com  
LOW  
POWER  
SCHOTTKY  
16  
1
PLASTIC  
N SUFFIX  
CASE 648  
Synchronous Load  
16  
Direct Overriding Clear  
Parallel to Serial Conversion  
1
SOIC  
D SUFFIX  
CASE 751B  
GUARANTEED OPERATING RANGES  
Symbol  
Parameter  
Supply Voltage  
Min  
4.75  
0
Typ  
5.0  
25  
Max  
5.25  
70  
Unit  
V
V
CC  
T
A
Operating Ambient  
Temperature Range  
°C  
16  
I
Output Current – High  
Output Current – Low  
–0.4  
8.0  
mA  
mA  
OH  
1
I
OL  
SOEIAJ  
M SUFFIX  
CASE 966  
ORDERING INFORMATION  
Device  
Package  
16 Pin DIP  
SOIC–16  
Shipping  
SN74LS166N  
SN74LS166D  
SN74LS166DR2  
SN74LS166M  
SN74LS166MEL  
2000 Units/Box  
38 Units/Rail  
2500/Tape & Reel  
See Note 1  
SOIC–16  
SOEIAJ–16  
SOEIAJ–16  
See Note 1  
1. For ordering information on the EIAJ version of  
the SOIC package, please contact your local  
ON Semiconductor representative.  
Semiconductor Components Industries, LLC, 2001  
1
Publication Order Number:  
October, 2001 – Rev. 7  
SN74LS166/D  

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