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SN74LS132DR2 PDF预览

SN74LS132DR2

更新时间: 2024-09-21 15:52:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 输入元件光电二极管逻辑集成电路触发器
页数 文件大小 规格书
3页 41K
描述
LS SERIES, QUAD 2-INPUT NAND GATE, PDSO14, SOIC-14

SN74LS132DR2 技术参数

生命周期:Transferred零件包装代码:SOIC
包装说明:SOP, SOP14,.25针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.28系列:LS
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
长度:8.65 mm负载电容(CL):15 pF
逻辑集成电路类型:NAND GATE最大I(ol):0.008 A
功能数量:4输入次数:2
端子数量:14最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL电源:5 V
最大电源电流(ICC):14 mAProp。Delay @ Nom-Sup:22 ns
传播延迟(tpd):22 ns认证状态:Not Qualified
施密特触发器:YES座面最大高度:1.75 mm
子类别:Gates最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
Base Number Matches:1

SN74LS132DR2 数据手册

 浏览型号SN74LS132DR2的Datasheet PDF文件第2页浏览型号SN74LS132DR2的Datasheet PDF文件第3页 
SN54/74LS132  
QUAD 2-INPUT  
SCHMITT TRIGGER NAND GATE  
The SN54/74LS132 contains four 2-Input NAND Gates which accept stan-  
dard TTL input signals and provide standard TTL output levels. They are ca-  
pableof transforming slowly changing input signals into sharply defined, jitter-  
free output signals. Additionally, they have greater noise margin than  
conventional NAND Gates.  
Each circuit contains a 2-input Schmitt trigger followed by a Darlington level  
shifterandaphasesplitterdrivingaTTLtotempoleoutput. TheSchmitttrigger  
uses positive feedback to effectively speed-up slow input transitions, and  
provide different input threshold voltages for positive and negative-going tran-  
sitions. This hysteresis between the positive-going and negative-going input  
thresholds (typically 800 mV) is determined internally by resistor ratios and is  
essentially insensitive to temperature and supply voltage variations. As long  
QUAD 2-INPUT  
SCHMITT TRIGGER NAND GATE  
LOW POWER SCHOTTKY  
J SUFFIX  
CERAMIC  
CASE 632-08  
as one input remains at a more positive voltage than V (MAX), the gate will  
T+  
respond to the transitions of the other input as shown in Figure 1.  
14  
1
LOGIC AND CONNECTION DIAGRAM  
DIP (TOP VIEW)  
N SUFFIX  
V
CC  
PLASTIC  
CASE 646-06  
14  
13  
12  
11  
10  
9
6
8
14  
1
D SUFFIX  
SOIC  
CASE 751A-02  
14  
1
1
2
3
4
5
7
GND  
ORDERING INFORMATION  
SN54LSXXXJ Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
5
4
V
= 5 V  
= 25°C  
CC  
T
A
3
2
1
0
0
0.4  
0.95  
1.2  
1.8  
2
V
, INPUT VOLTAGE (VOLTS)  
IN  
Figure 1. V versus V  
IN  
Transfer Function  
OUT  
FAST AND LS TTL DATA  
5-1  

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