5秒后页面跳转
捷配首页

Datasheet > SN74HC74-Q1
SN74HC74-Q1 PDF预览

SN74HC74-Q1

更新时间： 2024-11-19 09:14:19
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
9页 213K
描述
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND

阅读下载

中文翻译

获取价格

SN74HC74-Q1 数据手册

 浏览型号SN74HC74-Q1的Datasheet PDF文件第2页浏览型号SN74HC74-Q1的Datasheet PDF文件第3页浏览型号SN74HC74-Q1的Datasheet PDF文件第4页浏览型号SN74HC74-Q1的Datasheet PDF文件第5页浏览型号SN74HC74-Q1的Datasheet PDF文件第6页浏览型号SN74HC74-Q1的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢂꢃ ꢆꢇ ꢈ  
ꢉꢊꢋ ꢌ ꢉꢆꢍ ꢎꢏ ꢐ ꢏꢑ ꢀꢒ ꢍ ꢒꢓꢐ ꢆꢐꢉꢔ ꢐꢆꢍ ꢕꢒ ꢔ ꢔꢐ ꢕꢐꢉ ꢖꢌ ꢒꢏ ꢆ ꢖꢌꢑ ꢏ  
ꢗ ꢒꢍ ꢄ ꢅꢌ ꢐꢋꢕ ꢋꢁꢉ ꢏ ꢕꢐ ꢀ ꢐꢍ  
SCLS577 − MARCH 2004  
D OR PW PACKAGE  
(TOP VIEW)  
D
Qualification in Accordance With  
AEC-Q100  
†
D
Qualified for Automotive Applications  
1CLR  
1D  
V
CC  
2CLR  
1
2
3
4
5
6
7
14  
13  
D
Customer-Specific Configuration Control  
Can Be Supported Along With  
Major-Change Approval  
1CLK  
1PRE  
1Q  
12 2D  
11  
10  
9
2CLK  
2PRE  
2Q  
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive Up To 10 LSTTL Loads  
1Q  
8
GND  
2Q  
Low Power Consumption, 80-µA Max I  
Typical t = 15 ns  
pd  
4-mA Output Drive at 5 V  
CC  
Low Input Current of 1 µA Max  
†
Contact factory for details. Q100 qualification data available on  
request.  
description/ordering information  
The SN74HC74 device contains two independent D-type positive-edge-triggered flip-flops. A low level at the  
preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When  
PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred  
to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and  
is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed  
without affecting the levels at the outputs.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
PACKAGE  
T
A
SOIC − D  
Reel of 2500  
Reel of 2000  
SN74HC74QDRQ1  
HC74Q  
HC74Q  
−40°C to 125°C  
TSSOP − PW  
SN74HC74QPWRQ1  
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
PRE  
L
CLR  
CLK  
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
X
H
†
†
H
L
L
X
H
H
H
H
H
↑
H
L
L
H
↑
H
H
L
X
Q
Q
0
0
†
This configuration is nonstable; that is, it does not  
persist when PRE or CLR returns to its inactive  
(high) level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢏ
ꢏ
ꢕ
ꢑ
ꢧ
ꢉ
ꢢ
ꢊ
ꢅ
ꢠ
ꢍ
ꢡ
ꢒ
ꢛ
ꢑ
ꢙ
ꢁ
ꢚ
ꢉ
ꢋ
ꢍ
ꢋ
ꢘ
ꢙ
ꢣ
ꢚ
ꢛ
ꢡ
ꢜ
ꢝ
ꢞ
ꢞ
ꢟ
ꢟ
ꢘ
ꢘ
ꢛ
ꢛ
ꢙ
ꢙ
ꢘ
ꢠ
ꢠ
ꢤ
ꢡ
ꢢ
ꢜ
ꢜ
ꢣ
ꢣ
ꢙ
ꢟ
ꢞ
ꢝ
ꢠ
ꢠ
ꢛ
ꢚ
ꢤ
ꢍꢣ  
ꢢ
ꢥ
ꢠ
ꢦ
ꢘ
ꢡ
ꢞ
ꢠ
ꢟ
ꢘ
ꢟ
ꢛ
ꢜ
ꢙ
ꢢ
ꢧ
ꢞ
ꢙ
ꢟ
ꢟ
ꢣ
ꢠ
ꢨ
Copyright 2004, Texas Instruments Incorporated  
ꢜ
ꢛ
ꢡ
ꢟ
ꢛ
ꢜ
ꢝ
ꢟ
ꢛ
ꢠ
ꢤ
ꢘ
ꢚ
ꢘ
ꢡ
ꢣ
ꢜ
ꢟ
ꢩ
ꢟ
ꢣ
ꢜ
ꢛ
ꢚ
ꢪ
ꢞ
ꢒ
ꢙ
ꢝ
ꢣ
ꢠ
ꢟ
ꢞ
ꢙ
ꢧ
ꢞ
ꢜ
ꢧ
ꢫ
ꢞ
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
ꢜ
ꢜ
ꢞ
ꢙ
ꢟ
ꢬ
ꢨ
ꢏ
ꢜ
ꢛ
ꢧ
ꢢ
ꢡ
ꢟ
ꢘ
ꢛ
ꢙ
ꢤ
ꢜ
ꢛ
ꢡ
ꢣ
ꢠ
ꢠ
ꢘ
ꢙ
ꢭ
ꢧ
ꢛ
ꢣ
ꢠ
ꢙ
ꢛ
ꢟ
ꢙ
ꢣ
ꢡ
ꢣ
ꢠ
ꢠ
ꢞ
ꢜ
ꢘ
ꢦ
ꢬ
ꢘ
ꢙ
ꢡ
ꢦ
ꢢ
ꢧ
ꢣ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

下载PDF

SN74HC74-Q1 替代型号

型号 品牌 替代类型 描述 数据表
SN74HC74-EP TI

功能相似

 DUAL D-TYPE POSITIVE EDGE TRIGGERED FLIP-FLOP WITH CLEAR AND PRESET
SN74HC74 TI

功能相似

 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN54HC74 TI

功能相似

 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

与SN74HC74-Q1相关器件

型号 品牌 获取价格 描述 数据表
SN74HC74QDRG4Q1 TI

获取价格

 		具有清零和预设功能的汽车类双路 D 类正边沿触发触发器 | D | 14 | -40 to
SN74HC74QDRQ1 TI

获取价格

 		DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND
SN74HC74QPWRG4Q1 TI

获取价格

 		具有清零和预设功能的汽车类双路 D 类正边沿触发触发器 | PW | 14 | -40 t
SN74HC74QPWRQ1 TI

获取价格

 		DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOP WITH CLEAR AND
SN74HC75D TI

获取价格

 		4-Bit Bistable Latches 16-SOIC -40 to 85
SN74HC75D-00 TI

获取价格

 		HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDSO16
SN74HC75DR-00 TI

获取价格

 		HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDSO16
SN74HC75N TI

获取价格

 		4-Bit Bistable Latches 16-PDIP -40 to 85
SN74HC76N TI

获取价格

 		Dual J-K Flip-Flops with Preset and Clear 16-PDIP -40 to 85
SN74HC77D TI

获取价格

 		IC,LATCH,SINGLE,4-BIT,HC-CMOS,SOP,14PIN,PLASTIC

与SN74HC74-Q1相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证