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SN74HC367PWTE4 PDF预览

SN74HC367PWTE4

更新时间： 2024-11-19 20:27:55
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
20页 891K
描述
Bus Driver, HC/UH Series, 2-Func, 4-Bit, True Output, CMOS, PDSO16, GREEN, PLASTIC, TSSOP-16

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中文翻译

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SN74HC367PWTE4 技术参数

生命周期：Contact Manufacturer包装说明：TSSOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.56其他特性：ONE FUNCTION WITH TWO BITS
系列：HC/UHJESD-30 代码：R-PDSO-G16
长度：5 mm逻辑集成电路类型：BUS DRIVER
位数：4功能数量：2
端口数量：2端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）：150 ns座面最大高度：1.2 mm
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL宽度：4.4 mm
Base Number Matches：1

SN74HC367PWTE4 数据手册

 浏览型号SN74HC367PWTE4的Datasheet PDF文件第2页浏览型号SN74HC367PWTE4的Datasheet PDF文件第3页浏览型号SN74HC367PWTE4的Datasheet PDF文件第4页浏览型号SN74HC367PWTE4的Datasheet PDF文件第5页浏览型号SN74HC367PWTE4的Datasheet PDF文件第6页浏览型号SN74HC367PWTE4的Datasheet PDF文件第7页 
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SCLS309D − JANUARY 1996 − REVISED SEPTEMBER 2003  
SN54HC367 . . . J OR W PACKAGE  
SN74HC367 . . . D, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
Wide Operating Voltage Range of 2 V to 6 V  
High-Current 3-State Outputs Drive Bus  
Lines, Buffer Memory Address Registers,  
or Drive Up To 15 LSTTL Loads  
1OE  
1A1  
1Y1  
1A2  
1Y2  
1A3  
1Y3  
GND  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
2OE  
2A2  
2Y2  
D
D
D
D
D
True Outputs  
Low Power Consumption, 80-µA Max I  
CC  
Typical t = 10 ns  
pd  
6-mA Output Drive at 5 V  
12 2A1  
11  
10  
9
2Y1  
1A4  
1Y4  
Low Input Current of 1 µA Max  
description/ordering information  
SN54HC367 . . . FK PACKAGE  
(TOP VIEW)  
These hex buffers and line drivers are designed  
specifically to improve both the performance and  
density of 3-state memory address drivers, clock  
drivers, and bus-oriented receivers and  
transmitters. The ’HC367 devices are organized  
as dual 4-line and 2-line buffers/drivers with  
active-low output-enable (1OE and 2OE) inputs.  
When OE is low, the device passes noninverted  
data from the A inputs to the Y outputs. When OE  
is high, the outputs are in the high-impedance  
state.  
3
2
1
20 19  
18  
2A2  
2Y2  
NC  
1Y1  
1A2  
NC  
4
5
6
7
8
17  
16  
15 2A1  
14  
9 10 11 12 13  
1Y2  
1A3  
2Y1  
NC − No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − N  
Tube of 25  
Tube of 40  
Reel of 2500  
Reel of 250  
Reel of 2000  
Tube of 90  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC367N  
SN74HC367N  
SN74HC367D  
SN74HC367DR  
SN74HC367DT  
SN74HC367NSR  
SN74HC367PW  
SN74HC367PWR  
SN74HC367PWT  
SNJ54HC367J  
SNJ54HC367W  
SNJ54HC367FK  
SOIC − D  
SOP − NS  
HC367  
HC367  
−40°C to 85°C  
TSSOP − PW  
HC367  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC367J  
SNJ54HC367W  
SNJ54HC367FK  
−55°C to 125°C  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...20

中文翻译

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