ꢀꢁꢂ ꢃ ꢄ ꢅꢆ ꢇꢆ ꢆꢈꢉ
ꢊꢋꢌ ꢍ ꢎ ꢏꢇ ꢅꢋꢀ ꢀ ꢐꢑ ꢇꢄ ꢒ
ꢑꢇ ꢒ ꢕ ꢖꢗ ꢇꢙ ꢍ ꢏꢛꢌꢁꢇ ꢍ ꢏꢗꢏ ꢍ ꢀ ꢒꢑ ꢎꢇ ꢏꢛ
ꢓ
ꢔ
ꢕ
ꢖ
ꢗꢘ
ꢆ
ꢔ
ꢆ
ꢖ
ꢗ
ꢍ
ꢙ
ꢐ
ꢖ
ꢗ
ꢙ
ꢍ
ꢇ
ꢌ
ꢚ
ꢏ
ꢅ
ꢋ
ꢀ
ꢀ
ꢐ
ꢑ
ꢇꢄ
ꢒ
ꢐ
SCDS119A − JANUARY 2003 − REVISED OCTOBER 2003
D
D
Output Voltage Translation Tracks V
D
D
V
Operating Range From 2.3 V to 3.6 V
CC
CC
Supports Mixed-Mode Signal Operation On
All Data I/O Ports
− 5-V Input Down To 3.3-V Output Level
Data I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
D
D
D
D
Control Inputs Can be Driven by TTL or
5-V/3.3-V CMOS Outputs
Shift With 3.3-V V
CC
− 5-V/3.3-V Input Down To 2.5-V Output
Level Shift With 2.5-V V
I
Supports Partial-Power-Down Mode
off
CC
Operation
D
D
D
D
D
D
5-V Tolerant I/Os With Device Powered-Up
or Powered-Down
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bidirectional Data Flow, With Near-Zero
Propagation Delay
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
Low ON-State Resistance (r
)
on
Characteristics (r = 5 Ω Typical)
on
− 1000-V Charged-Device Model (C101)
Low Input/Output Capacitance Minimizes
D
D
Supports Digital Applications: Level
Translation, USB Interface, Bus Isolation
Loading (C
= 4.5 pF Typical)
io(OFF)
Data and Control Inputs Provide
Undershoot Clamp Diodes
Ideal for Low-Power Portable Equipment
Low Power Consumption
(I
= 20 µA Max)
CC
DCT OR DCU PACKAGE
(TOP VIEW)
1OE
1A
1B
1
2
3
4
8
7
6
5
V
CC
2OE
2B
2A
GND
description/ordering information
The SN74CB3T3306 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (r ),
on
allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O
ports by providing voltage translation that tracks V . The SN74CB3T3306 supports systems using 5-V TTL,
CC
3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1).
The SN74CB3T3306 is organized as two 1-bit bus switches with separate ouput-enable (1OE, 2OE) inputs. It
can be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is low, the associated 1-bit bus switch
is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high,
the associated 1-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
†
PACKAGE
T
A
‡
MARKING
WA6_ _ _
WA6_
SSOP − DCT
Tape and reel SN74CB3T3306DCTR
Tape and reel SN74CB3T3306DCUR
−40°C to 85°C
VSSOP − DCU
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
DCT: The actual top-side marking has three additional characters that designate the year, month, and
assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢜ
ꢜ
ꢛ
ꢙ
ꢬ
ꢊ
ꢧ
ꢋ
ꢄ
ꢥ
ꢇ
ꢦ
ꢑ
ꢠ
ꢙ
ꢞ
ꢁ
ꢟ
ꢊ
ꢌ
ꢇ
ꢌ
ꢝ
ꢞ
ꢨ
ꢟ
ꢠ
ꢦ
ꢡ
ꢢ
ꢣ
ꢣ
ꢤ
ꢤ
ꢝ
ꢝ
ꢠ
ꢠ
ꢞ
ꢞ
ꢝ
ꢥ
ꢥ
ꢩ
ꢦ
ꢧ
ꢡ
ꢡ
ꢨ
ꢨ
ꢞ
ꢤ
ꢣ
ꢢ
ꢥ
ꢥ
ꢠ
ꢟ
ꢩ
ꢇꢨ
ꢧ
ꢪ
ꢥ
ꢫ
ꢝ
ꢦ
ꢣ
ꢥ
ꢤ
ꢝ
ꢤ
ꢠ
ꢡ
ꢞ
ꢧ
ꢬ
ꢣ
ꢞ
ꢤ
ꢤ
ꢨ
ꢥ
ꢔ
Copyright 2003, Texas Instruments Incorporated
ꢡ
ꢠ
ꢦ
ꢤ
ꢠ
ꢡ
ꢢ
ꢤ
ꢠ
ꢥ
ꢩ
ꢝ
ꢟ
ꢝ
ꢦ
ꢨ
ꢡ
ꢤ
ꢭ
ꢤ
ꢨ
ꢡ
ꢠ
ꢟ
ꢮ
ꢣ
ꢑ
ꢞ
ꢢ
ꢨ
ꢥ
ꢤ
ꢣ
ꢞ
ꢬ
ꢣ
ꢡ
ꢬ
ꢯ
ꢣ
ꢤ ꢨ ꢥ ꢤꢝ ꢞꢱ ꢠꢟ ꢣ ꢫꢫ ꢩꢣ ꢡ ꢣ ꢢ ꢨ ꢤ ꢨ ꢡ ꢥ ꢔ
ꢡ
ꢡ
ꢣ
ꢞ
ꢤ
ꢰ
ꢔ
ꢜ
ꢡ
ꢠ
ꢬ
ꢧ
ꢦ
ꢤ
ꢝ
ꢠ
ꢞ
ꢩ
ꢡ
ꢠ
ꢦ
ꢨ
ꢥ
ꢥ
ꢝ
ꢞ
ꢱ
ꢬ
ꢠ
ꢨ
ꢥ
ꢞ
ꢠ
ꢤ
ꢞ
ꢨ
ꢦ
ꢨ
ꢥ
ꢥ
ꢣ
ꢡ
ꢝ
ꢫ
ꢰ
ꢝ
ꢞ
ꢦ
ꢫ
ꢧ
ꢬ
ꢨ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265